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(parent: d8c950d) | patch
core: Allow writing to more PCI config space registers
authorJan Kiszka <jan.kiszka@siemens.com>
Wed, 23 Jul 2014 18:24:13 +0000 (20:24 +0200)
committerJan Kiszka <jan.kiszka@siemens.com>
Sat, 26 Jul 2014 11:10:14 +0000 (13:10 +0200)
commit30b6db2dc3f285ebf63b5c453c0e8ac3512d9816
treeaf09ea4934282a8f97d091ea3c73ea693cf941b0tree | snapshot
parentd8c950d22a7e2212820f4e23a6f581bfd1f877d7commit | diff
core: Allow writing to more PCI config space registers

Enable write access to the Master Latency Timer (non-functional for
PCIe) and the Cacheline Size (no misuse potential identified).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
hypervisor/pci.c diff | blob | history