arm: hide TLB flush behind a macro

[jailhouse.git] / hypervisor / arch / arm / mmu_cell.c

diff --git a/hypervisor/arch/arm/mmu_cell.c b/hypervisor/arch/arm/mmu_cell.c
index fb5ad835e502d309b0deafb53b38b778343b99b7..d16c5ea1f682c9b46675d48f5ce43000c8bd05ec 100644 (file)
--- a/hypervisor/arch/arm/mmu_cell.c
+++ b/hypervisor/arch/arm/mmu_cell.c
@@ -77,12 +77,7 @@ int arch_mmu_cpu_cell_init(struct per_cpu *cpu_data)
        struct cell *cell = cpu_data->cell;
        unsigned long cell_table = paging_hvirt2phys(cell->arch.mm.root_table);
        u64 vttbr = 0;
-       u32 vtcr = T0SZ
-               | SL0 << TCR_SL0_SHIFT
-               | (TCR_RGN_WB_WA << TCR_IRGN0_SHIFT)
-               | (TCR_RGN_WB_WA << TCR_ORGN0_SHIFT)
-               | (TCR_INNER_SHAREABLE << TCR_SH0_SHIFT)
-               | VTCR_RES1;
+       u32 vtcr = VTCR_CELL;
 
        if (cell->id > 0xff) {
                panic_printk("No cell ID available\n");
@@ -112,7 +107,7 @@ void arch_cpu_tlb_flush(struct per_cpu *cpu_data)
         * Invalidate all stage-1 and 2 TLB entries for the current VMID
         * ERET will ensure completion of these ops
         */
-       arm_write_sysreg(TLBIALL, 1);
+       tlb_flush_guest();
        dsb(nsh);
        cpu_data->flush_vcpu_caches = false;
 }