arm: hide TLB flush behind a macro

Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.

Signed-off-by: Antonios Motakis <antonios.motakis@huawei.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/arch/arm/include/asm/processor.h b/hypervisor/arch/arm/include/asm/processor.h
index c6144a71eb2fbaf725fea77e865cbb7ce51ccdaa..907a28e67de37d6cb82055ba19fb9d763322210a 100644 (file)
--- a/hypervisor/arch/arm/include/asm/processor.h
+++ b/hypervisor/arch/arm/include/asm/processor.h
@@ -197,6 +197,8 @@ static inline bool is_el2(void)
        return (psr & PSR_MODE_MASK) == PSR_HYP_MODE;
 }
 
+#define tlb_flush_guest()      arm_write_sysreg(TLBIALL, 1)
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */

diff --git a/hypervisor/arch/arm/mmu_cell.c b/hypervisor/arch/arm/mmu_cell.c
index d3031def7cfe98f487232d701040b7126a0ae6d9..d16c5ea1f682c9b46675d48f5ce43000c8bd05ec 100644 (file)
--- a/hypervisor/arch/arm/mmu_cell.c
+++ b/hypervisor/arch/arm/mmu_cell.c
@@ -107,7 +107,7 @@ void arch_cpu_tlb_flush(struct per_cpu *cpu_data)
         * Invalidate all stage-1 and 2 TLB entries for the current VMID
         * ERET will ensure completion of these ops
         */
-       arm_write_sysreg(TLBIALL, 1);
+       tlb_flush_guest();
        dsb(nsh);
        cpu_data->flush_vcpu_caches = false;
 }