hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 static bool has_avic, has_assists, has_flush_by_asid;
  43
  44 static const struct segment invalid_seg;
  45
  46 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  47
  48 /* bit cleared: direct access allowed */
  49 // TODO: convert to whitelist
  50 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  51         [ SVM_MSRPM_0000 ] = {
  52                 [      0/4 ...  0x017/4 ] = 0,
  53                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  54                 [  0x01c/4 ...  0x273/4 ] = 0,
  55                 [  0x274/4 ...  0x277/4 ] = 0xc0, /* 0x277 (rw) */
  56                 [  0x278/4 ...  0x2fb/4 ] = 0,
  57                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  58                 [  0x300/4 ...  0x7ff/4 ] = 0,
  59                 /* x2APIC MSRs - emulated if not present */
  60                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  61                 [  0x804/4 ...  0x807/4 ] = 0,
  62                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  63                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  64                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  65                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  66                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  67                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  68                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  69                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  70                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  71                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  72                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  73                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  74                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  75                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  76                 [  0x840/4 ... 0x1fff/4 ] = 0,
  77         },
  78         [ SVM_MSRPM_C000 ] = {
  79                 [      0/4 ...  0x07f/4 ] = 0,
  80                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  81                 [  0x084/4 ... 0x1fff/4 ] = 0
  82         },
  83         [ SVM_MSRPM_C001 ] = {
  84                 [      0/4 ... 0x1fff/4 ] = 0,
  85         },
  86         [ SVM_MSRPM_RESV ] = {
  87                 [      0/4 ... 0x1fff/4 ] = 0,
  88         }
  89 };
  90
  91 /* This page is mapped so the code begins at 0x000ffff0 */
  92 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  93         [0xff0] = 0xfa, /* 1: cli */
  94         [0xff1] = 0xf4, /*    hlt */
  95         [0xff2] = 0xeb,
  96         [0xff3] = 0xfc  /*    jmp 1b */
  97 };
  98
  99 static void *parked_mode_npt;
 100
 101 static void *avic_page;
 102
 103 static int svm_check_features(void)
 104 {
 105         /* SVM is available */
 106         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 107                 return trace_error(-ENODEV);
 108
 109         /* Nested paging */
 110         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 111                 return trace_error(-EIO);
 112
 113         /* Decode assists */
 114         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 115                 has_assists = true;
 116
 117         /* AVIC support */
 118         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 119                 has_avic = true;
 120
 121         /* TLB Flush by ASID support */
 122         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 123                 has_flush_by_asid = true;
 124
 125         return 0;
 126 }
 127
 128 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 129                                      const struct desc_table_reg *dtr)
 130 {
 131         struct svm_segment tmp = { 0 };
 132
 133         if (dtr) {
 134                 tmp.base = dtr->base;
 135                 tmp.limit = dtr->limit & 0xffff;
 136         }
 137
 138         *svm_segment = tmp;
 139 }
 140
 141 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
 142 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 143                                          const struct segment *segment)
 144 {
 145         u32 ar;
 146
 147         svm_segment->selector = segment->selector;
 148
 149         if (segment->access_rights == 0x10000) {
 150                 svm_segment->access_rights = 0;
 151         } else {
 152                 ar = segment->access_rights;
 153                 svm_segment->access_rights =
 154                         ((ar & 0xf000) >> 4) | (ar & 0x00ff);
 155         }
 156
 157         svm_segment->limit = segment->limit;
 158         svm_segment->base = segment->base;
 159 }
 160
 161 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 162 {
 163         /* No real need for this function; used for consistency with vmx.c */
 164         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 165         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 166
 167         return true;
 168 }
 169
 170 static int vmcb_setup(struct per_cpu *cpu_data)
 171 {
 172         struct vmcb *vmcb = &cpu_data->vmcb;
 173
 174         memset(vmcb, 0, sizeof(struct vmcb));
 175
 176         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 177         vmcb->cr3 = cpu_data->linux_cr3;
 178         vmcb->cr4 = cpu_data->linux_cr4;
 179
 180         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 181         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 182         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 183         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 184         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 185         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 186         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 187
 188         set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
 189         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 190         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 191
 192         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 193
 194         vmcb->rflags = 0x02;
 195         /* Indicate success to the caller of arch_entry */
 196         vmcb->rax = 0;
 197         vmcb->rsp = cpu_data->linux_sp +
 198                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 199         vmcb->rip = cpu_data->linux_ip;
 200
 201         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 202         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 203         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 204         vmcb->star = read_msr(MSR_STAR);
 205         vmcb->lstar = read_msr(MSR_LSTAR);
 206         vmcb->cstar = read_msr(MSR_CSTAR);
 207         vmcb->sfmask = read_msr(MSR_SFMASK);
 208         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 209
 210         vmcb->dr6 = 0x00000ff0;
 211         vmcb->dr7 = 0x00000400;
 212
 213         /* Make the hypervisor visible */
 214         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 215
 216         vmcb->g_pat = cpu_data->pat;
 217
 218         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 219         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 220         /* TODO: Do we need this for SVM ? */
 221         /* vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID; */
 222         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 223         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 224         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 225
 226         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 227         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 228
 229         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 230
 231         vmcb->np_enable = 1;
 232         /* No more than one guest owns the CPU */
 233         vmcb->guest_asid = 1;
 234
 235         /* TODO: Setup AVIC */
 236
 237         /* Explicitly mark all of the state as new */
 238         vmcb->clean_bits = 0;
 239
 240         return svm_set_cell_config(cpu_data->cell, vmcb);
 241 }
 242
 243 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 244                                      unsigned long gphys,
 245                                      unsigned long flags)
 246 {
 247         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 248                         gphys, flags);
 249 }
 250
 251 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 252 {
 253         /* See APMv2, Section 15.25.5 */
 254         *pte = (next_pt & 0x000ffffffffff000UL) |
 255                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 256 }
 257
 258 int vcpu_vendor_init(void)
 259 {
 260         struct paging_structures parking_pt;
 261         unsigned long vm_cr;
 262         int err, n;
 263
 264         err = svm_check_features();
 265         if (err)
 266                 return err;
 267
 268         vm_cr = read_msr(MSR_VM_CR);
 269         if (vm_cr & VM_CR_SVMDIS)
 270                 /* SVM disabled in BIOS */
 271                 return trace_error(-EPERM);
 272
 273         /* Nested paging is the same as the native one */
 274         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 275         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 276                 npt_paging[n].set_next_pt = npt_set_next_pt;
 277
 278         /* Map guest parking code (shared between cells and CPUs) */
 279         parking_pt.root_paging = npt_paging;
 280         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 281         if (!parked_mode_npt)
 282                 return -ENOMEM;
 283         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 284                             PAGE_SIZE, 0x000ff000,
 285                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 286                             PAGING_NON_COHERENT);
 287         if (err)
 288                 return err;
 289
 290         /* This is always false for AMD now (except in nested SVM);
 291            see Sect. 16.3.1 in APMv2 */
 292         if (using_x2apic) {
 293                 /* allow direct x2APIC access except for ICR writes */
 294                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 295                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 296                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 297         } else {
 298                 if (has_avic) {
 299                         avic_page = page_alloc(&remap_pool, 1);
 300                         if (!avic_page)
 301                                 return trace_error(-ENOMEM);
 302                 }
 303         }
 304
 305         return vcpu_cell_init(&root_cell);
 306 }
 307
 308 int vcpu_vendor_cell_init(struct cell *cell)
 309 {
 310         u64 flags;
 311         int err;
 312
 313         /* allocate iopm (two 4-K pages + 3 bits) */
 314         cell->svm.iopm = page_alloc(&mem_pool, 3);
 315         if (!cell->svm.iopm)
 316                 return -ENOMEM;
 317
 318         /* build root NPT of cell */
 319         cell->svm.npt_structs.root_paging = npt_paging;
 320         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 321         if (!cell->svm.npt_structs.root_table)
 322                 return -ENOMEM;
 323
 324         if (!has_avic) {
 325                 /*
 326                  * Map xAPIC as is; reads are passed, writes are trapped.
 327                  */
 328                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 329                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 330                                     PAGE_SIZE, XAPIC_BASE,
 331                                     flags,
 332                                     PAGING_NON_COHERENT);
 333         } else {
 334                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 335                 err = paging_create(&cell->svm.npt_structs,
 336                                     paging_hvirt2phys(avic_page),
 337                                     PAGE_SIZE, XAPIC_BASE,
 338                                     flags,
 339                                     PAGING_NON_COHERENT);
 340         }
 341
 342         return err;
 343 }
 344
 345 int vcpu_map_memory_region(struct cell *cell,
 346                            const struct jailhouse_memory *mem)
 347 {
 348         u64 phys_start = mem->phys_start;
 349         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 350
 351         if (mem->flags & JAILHOUSE_MEM_READ)
 352                 flags |= PAGE_FLAG_PRESENT;
 353         if (mem->flags & JAILHOUSE_MEM_WRITE)
 354                 flags |= PAGE_FLAG_RW;
 355         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 356                 flags |= PAGE_FLAG_NOEXECUTE;
 357         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 358                 phys_start = paging_hvirt2phys(&cell->comm_page);
 359
 360         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 361                              mem->virt_start, flags, PAGING_NON_COHERENT);
 362 }
 363
 364 int vcpu_unmap_memory_region(struct cell *cell,
 365                              const struct jailhouse_memory *mem)
 366 {
 367         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 368                               mem->size, PAGING_NON_COHERENT);
 369 }
 370
 371 void vcpu_vendor_cell_exit(struct cell *cell)
 372 {
 373         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 374                        PAGING_NON_COHERENT);
 375         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 376 }
 377
 378 int vcpu_init(struct per_cpu *cpu_data)
 379 {
 380         unsigned long efer;
 381         int err;
 382
 383         err = svm_check_features();
 384         if (err)
 385                 return err;
 386
 387         efer = read_msr(MSR_EFER);
 388         if (efer & EFER_SVME)
 389                 return trace_error(-EBUSY);
 390
 391         efer |= EFER_SVME;
 392         write_msr(MSR_EFER, efer);
 393
 394         cpu_data->svm_state = SVMON;
 395
 396         if (!vmcb_setup(cpu_data))
 397                 return trace_error(-EIO);
 398
 399         /*
 400          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 401          * set the values of reserved bits to the values found during the
 402          * previous CR0 read."
 403          * But we want to avoid surprises with new features unknown to us but
 404          * set by Linux. So check if any assumed revered bit was set and bail
 405          * out if so.
 406          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 407          */
 408         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 409                 return -EIO;
 410
 411         /* bring CR0 and CR4 into well-defined states */
 412         write_cr0(X86_CR0_HOST_STATE);
 413         write_cr4(X86_CR4_HOST_STATE);
 414
 415         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 416
 417         return 0;
 418 }
 419
 420 void vcpu_exit(struct per_cpu *cpu_data)
 421 {
 422         unsigned long efer;
 423
 424         if (cpu_data->svm_state == SVMOFF)
 425                 return;
 426
 427         cpu_data->svm_state = SVMOFF;
 428
 429         /* We are leaving - set the GIF */
 430         asm volatile ("stgi" : : : "memory");
 431
 432         efer = read_msr(MSR_EFER);
 433         efer &= ~EFER_SVME;
 434         write_msr(MSR_EFER, efer);
 435
 436         write_msr(MSR_VM_HSAVE_PA, 0);
 437 }
 438
 439 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 440 {
 441         unsigned long vmcb_pa, host_stack;
 442
 443         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 444         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 445
 446         /* We enter Linux at the point arch_entry would return to as well.
 447          * rax is cleared to signal success to the caller. */
 448         asm volatile(
 449                 "clgi\n\t"
 450                 "mov (%%rdi),%%r15\n\t"
 451                 "mov 0x8(%%rdi),%%r14\n\t"
 452                 "mov 0x10(%%rdi),%%r13\n\t"
 453                 "mov 0x18(%%rdi),%%r12\n\t"
 454                 "mov 0x20(%%rdi),%%rbx\n\t"
 455                 "mov 0x28(%%rdi),%%rbp\n\t"
 456                 "mov %0, %%rax\n\t"
 457                 "vmload %%rax\n\t"
 458                 "vmrun %%rax\n\t"
 459                 "vmsave %%rax\n\t"
 460                 /* Restore hypervisor stack */
 461                 "mov %2, %%rsp\n\t"
 462                 "jmp svm_vmexit"
 463                 : /* no output */
 464                 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
 465                 : "memory", "r15", "r14", "r13", "r12",
 466                   "rbx", "rbp", "rax", "cc");
 467         __builtin_unreachable();
 468 }
 469
 470 void __attribute__((noreturn))
 471 vcpu_deactivate_vmm(struct registers *guest_regs)
 472 {
 473         struct per_cpu *cpu_data = this_cpu_data();
 474         struct vmcb *vmcb = &cpu_data->vmcb;
 475         unsigned long *stack = (unsigned long *)vmcb->rsp;
 476         unsigned long linux_ip = vmcb->rip;
 477
 478         /*
 479          * Restore the MSRs.
 480          *
 481          * XXX: One could argue this is better to be done in
 482          * arch_cpu_restore(), however, it would require changes
 483          * to cpu_data to store STAR and friends.
 484          */
 485         write_msr(MSR_STAR, vmcb->star);
 486         write_msr(MSR_LSTAR, vmcb->lstar);
 487         write_msr(MSR_CSTAR, vmcb->cstar);
 488         write_msr(MSR_SFMASK, vmcb->sfmask);
 489         write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
 490
 491         cpu_data->linux_cr0 = vmcb->cr0;
 492         cpu_data->linux_cr3 = vmcb->cr3;
 493
 494         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 495         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 496         cpu_data->linux_idtr.base = vmcb->idtr.base;
 497         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 498
 499         cpu_data->linux_cs.selector = vmcb->cs.selector;
 500
 501         cpu_data->linux_tss.selector = vmcb->tr.selector;
 502
 503         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 504         cpu_data->linux_fs.base = vmcb->fs.base;
 505         cpu_data->linux_gs.base = vmcb->gs.base;
 506
 507         cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
 508         cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
 509         cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
 510
 511         cpu_data->linux_ds.selector = vmcb->ds.selector;
 512         cpu_data->linux_es.selector = vmcb->es.selector;
 513         cpu_data->linux_fs.selector = vmcb->fs.selector;
 514         cpu_data->linux_gs.selector = vmcb->gs.selector;
 515
 516         arch_cpu_restore(cpu_data, 0);
 517
 518         stack--;
 519         *stack = linux_ip;
 520
 521         asm volatile (
 522                 "mov %%rbx,%%rsp\n\t"
 523                 "pop %%r15\n\t"
 524                 "pop %%r14\n\t"
 525                 "pop %%r13\n\t"
 526                 "pop %%r12\n\t"
 527                 "pop %%r11\n\t"
 528                 "pop %%r10\n\t"
 529                 "pop %%r9\n\t"
 530                 "pop %%r8\n\t"
 531                 "pop %%rdi\n\t"
 532                 "pop %%rsi\n\t"
 533                 "pop %%rbp\n\t"
 534                 "add $8,%%rsp\n\t"
 535                 "pop %%rbx\n\t"
 536                 "pop %%rdx\n\t"
 537                 "pop %%rcx\n\t"
 538                 "mov %%rax,%%rsp\n\t"
 539                 "xor %%rax,%%rax\n\t"
 540                 "ret"
 541                 : : "a" (stack), "b" (guest_regs));
 542         __builtin_unreachable();
 543 }
 544
 545 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 546 {
 547         struct vmcb *vmcb = &cpu_data->vmcb;
 548         unsigned long val;
 549         bool ok = true;
 550
 551         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 552         vmcb->cr3 = 0;
 553         vmcb->cr4 = 0;
 554
 555         vmcb->rflags = 0x02;
 556
 557         val = 0;
 558         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 559                 val = 0xfff0;
 560                 sipi_vector = 0xf0;
 561         }
 562         vmcb->rip = val;
 563         vmcb->rsp = 0;
 564
 565         vmcb->cs.selector = sipi_vector << 8;
 566         vmcb->cs.base = sipi_vector << 12;
 567         vmcb->cs.limit = 0xffff;
 568         vmcb->cs.access_rights = 0x009b;
 569
 570         vmcb->ds.selector = 0;
 571         vmcb->ds.base = 0;
 572         vmcb->ds.limit = 0xffff;
 573         vmcb->ds.access_rights = 0x0093;
 574
 575         vmcb->es.selector = 0;
 576         vmcb->es.base = 0;
 577         vmcb->es.limit = 0xffff;
 578         vmcb->es.access_rights = 0x0093;
 579
 580         vmcb->fs.selector = 0;
 581         vmcb->fs.base = 0;
 582         vmcb->fs.limit = 0xffff;
 583         vmcb->fs.access_rights = 0x0093;
 584
 585         vmcb->gs.selector = 0;
 586         vmcb->gs.base = 0;
 587         vmcb->gs.limit = 0xffff;
 588         vmcb->gs.access_rights = 0x0093;
 589
 590         vmcb->ss.selector = 0;
 591         vmcb->ss.base = 0;
 592         vmcb->ss.limit = 0xffff;
 593         vmcb->ss.access_rights = 0x0093;
 594
 595         vmcb->tr.selector = 0;
 596         vmcb->tr.base = 0;
 597         vmcb->tr.limit = 0xffff;
 598         vmcb->tr.access_rights = 0x008b;
 599
 600         vmcb->ldtr.selector = 0;
 601         vmcb->ldtr.base = 0;
 602         vmcb->ldtr.limit = 0xffff;
 603         vmcb->ldtr.access_rights = 0x0082;
 604
 605         vmcb->gdtr.selector = 0;
 606         vmcb->gdtr.base = 0;
 607         vmcb->gdtr.limit = 0xffff;
 608         vmcb->gdtr.access_rights = 0;
 609
 610         vmcb->idtr.selector = 0;
 611         vmcb->idtr.base = 0;
 612         vmcb->idtr.limit = 0xffff;
 613         vmcb->idtr.access_rights = 0;
 614
 615         vmcb->efer = EFER_SVME;
 616
 617         /* These MSRs are undefined on reset */
 618         vmcb->star = 0;
 619         vmcb->lstar = 0;
 620         vmcb->cstar = 0;
 621         vmcb->sfmask = 0;
 622         vmcb->sysenter_cs = 0;
 623         vmcb->sysenter_eip = 0;
 624         vmcb->sysenter_esp = 0;
 625         vmcb->kerngsbase = 0;
 626
 627         vmcb->dr7 = 0x00000400;
 628
 629         /* Almost all of the guest state changed */
 630         vmcb->clean_bits = 0;
 631
 632         ok &= svm_set_cell_config(cpu_data->cell, vmcb);
 633
 634         /* This is always false, but to be consistent with vmx.c... */
 635         if (!ok) {
 636                 panic_printk("FATAL: CPU reset failed\n");
 637                 panic_stop();
 638         }
 639 }
 640
 641 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 642 {
 643         struct per_cpu *cpu_data = this_cpu_data();
 644         struct vmcb *vmcb = &cpu_data->vmcb;
 645         vmcb->rip += inst_len;
 646 }
 647
 648 static void update_efer(struct per_cpu *cpu_data)
 649 {
 650         struct vmcb *vmcb = &cpu_data->vmcb;
 651         unsigned long efer = vmcb->efer;
 652
 653         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 654                 return;
 655
 656         efer |= EFER_LMA;
 657
 658         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 659         if ((vmcb->efer ^ efer) & EFER_LMA)
 660                 vcpu_tlb_flush();
 661
 662         vmcb->efer = efer;
 663         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 664 }
 665
 666 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 667 {
 668         struct per_cpu *cpu_data = this_cpu_data();
 669         struct vmcb *vmcb = &cpu_data->vmcb;
 670
 671         if (vmcb->efer & EFER_LMA) {
 672                 pg_structs->root_paging = x86_64_paging;
 673                 pg_structs->root_table_gphys =
 674                         vmcb->cr3 & 0x000ffffffffff000UL;
 675         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 676                    !(vmcb->cr4 & X86_CR4_PAE)) {
 677                 pg_structs->root_paging = i386_paging;
 678                 pg_structs->root_table_gphys =
 679                         vmcb->cr3 & 0xfffff000UL;
 680         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 681                 /*
 682                  * Can be in non-paged protected mode as well, but
 683                  * the translation mechanism will stay the same ayway.
 684                  */
 685                 pg_structs->root_paging = realmode_paging;
 686                 /*
 687                  * This will make paging_get_guest_pages map the page
 688                  * that also contains the bootstrap code and, thus, is
 689                  * always present in a cell.
 690                  */
 691                 pg_structs->root_table_gphys = 0xff000;
 692         } else {
 693                 printk("FATAL: Unsupported paging mode\n");
 694                 return false;
 695         }
 696         return true;
 697 }
 698
 699 void vcpu_vendor_set_guest_pat(unsigned long val)
 700 {
 701         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 702
 703         vmcb->g_pat = val;
 704         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 705 }
 706
 707 struct parse_context {
 708         unsigned int remaining;
 709         unsigned int size;
 710         unsigned long cs_base;
 711         const u8 *inst;
 712 };
 713
 714 static bool ctx_advance(struct parse_context *ctx,
 715                         unsigned long *pc,
 716                         struct guest_paging_structures *pg_structs)
 717 {
 718         if (!ctx->size) {
 719                 ctx->size = ctx->remaining;
 720                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 721                                           &ctx->size);
 722                 if (!ctx->inst)
 723                         return false;
 724                 ctx->remaining -= ctx->size;
 725                 *pc += ctx->size;
 726         }
 727         return true;
 728 }
 729
 730 static bool x86_parse_mov_to_cr(struct per_cpu *cpu_data,
 731                                 unsigned long pc,
 732                                 unsigned char reg,
 733                                 unsigned long *gpr)
 734 {
 735         struct guest_paging_structures pg_structs;
 736         struct vmcb *vmcb = &cpu_data->vmcb;
 737         struct parse_context ctx = {};
 738         /* No prefixes are supported yet */
 739         u8 opcodes[] = {0x0f, 0x22}, modrm;
 740         bool ok = false;
 741         int n;
 742
 743         ctx.remaining = ARRAY_SIZE(opcodes);
 744         if (!vcpu_get_guest_paging_structs(&pg_structs))
 745                 goto out;
 746         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 747
 748         if (!ctx_advance(&ctx, &pc, &pg_structs))
 749                 goto out;
 750
 751         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
 752                 if (*(ctx.inst) != opcodes[n])
 753                         goto out;
 754                 if (!ctx_advance(&ctx, &pc, &pg_structs))
 755                         goto out;
 756         }
 757
 758         if (!ctx_advance(&ctx, &pc, &pg_structs))
 759                 goto out;
 760
 761         modrm = *(ctx.inst);
 762
 763         if (((modrm & 0x38) >> 3) != reg)
 764                 goto out;
 765
 766         if (gpr)
 767                 *gpr = (modrm & 0x7);
 768
 769         ok = true;
 770 out:
 771         return ok;
 772 }
 773
 774 /*
 775  * XXX: The only visible reason to have this function (vmx.c consistency
 776  * aside) is to prevent cells from setting invalid CD+NW combinations that
 777  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 778  * altogether?
 779  */
 780 static bool svm_handle_cr(struct registers *guest_regs,
 781                           struct per_cpu *cpu_data)
 782 {
 783         struct vmcb *vmcb = &cpu_data->vmcb;
 784         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 785         unsigned long reg = -1, val, bits;
 786         bool ok = true;
 787
 788         if (has_assists) {
 789                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 790                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 791                         ok = false;
 792                         goto out;
 793                 }
 794                 reg = vmcb->exitinfo1 & 0x07;
 795         } else {
 796                 if (!x86_parse_mov_to_cr(cpu_data, vmcb->rip, 0, &reg)) {
 797                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 798                         ok = false;
 799                         goto out;
 800                 }
 801         };
 802
 803         if (reg == 4)
 804                 val = vmcb->rsp;
 805         else
 806                 val = ((unsigned long *)guest_regs)[15 - reg];
 807
 808         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 809         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 810         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 811         if ((val ^ vmcb->cr0) & bits)
 812                 vcpu_tlb_flush();
 813         /* TODO: better check for #GP reasons */
 814         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 815         if (val & X86_CR0_PG)
 816                 update_efer(cpu_data);
 817         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 818
 819 out:
 820         return ok;
 821 }
 822
 823 static bool svm_handle_msr_write(struct registers *guest_regs,
 824                 struct per_cpu *cpu_data)
 825 {
 826         struct vmcb *vmcb = &cpu_data->vmcb;
 827         unsigned long efer;
 828
 829         if (guest_regs->rcx == MSR_EFER) {
 830                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 831                 efer = get_wrmsr_value(guest_regs) | EFER_SVME;
 832                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 833                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 834                         vcpu_tlb_flush();
 835                 vmcb->efer = efer;
 836                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 837                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 838                 return true;
 839         }
 840
 841         return vcpu_handle_msr_write(guest_regs);
 842 }
 843
 844 /*
 845  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 846  * be treated separately in svm_handle_avic_access().
 847  */
 848 static bool svm_handle_apic_access(struct registers *guest_regs,
 849                                    struct per_cpu *cpu_data)
 850 {
 851         struct vmcb *vmcb = &cpu_data->vmcb;
 852         struct guest_paging_structures pg_structs;
 853         unsigned int inst_len, offset;
 854         bool is_write;
 855
 856         /* The caller is responsible for sanity checks */
 857         is_write = !!(vmcb->exitinfo1 & 0x2);
 858         offset = vmcb->exitinfo2 - XAPIC_BASE;
 859
 860         if (offset & 0x00f)
 861                 goto out_err;
 862
 863         if (!vcpu_get_guest_paging_structs(&pg_structs))
 864                 goto out_err;
 865
 866         inst_len = apic_mmio_access(guest_regs, cpu_data, vmcb->rip,
 867                                     &pg_structs, offset >> 4, is_write);
 868         if (!inst_len)
 869                 goto out_err;
 870
 871         vcpu_skip_emulated_instruction(inst_len);
 872         return true;
 873
 874 out_err:
 875         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 876                      offset, is_write);
 877         return false;
 878 }
 879
 880 static void dump_guest_regs(struct registers *guest_regs, struct vmcb *vmcb)
 881 {
 882         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 883                      vmcb->rsp, vmcb->rflags);
 884         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 885                      guest_regs->rbx, guest_regs->rcx);
 886         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 887                      guest_regs->rsi, guest_regs->rdi);
 888         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 889                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 890                      !!(vmcb->efer & EFER_LMA));
 891         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 892                      vmcb->cr3, vmcb->cr4);
 893         panic_printk("EFER: %p\n", vmcb->efer);
 894 }
 895
 896 static void svm_get_vcpu_pf_intercept(struct per_cpu *cpu_data,
 897                                       struct vcpu_pf_intercept *out)
 898 {
 899         struct vmcb *vmcb = &cpu_data->vmcb;
 900
 901         out->phys_addr = vmcb->exitinfo2;
 902         out->is_write = !!(vmcb->exitinfo1 & 0x2);
 903 }
 904
 905 static void svm_get_vcpu_io_intercept(struct per_cpu *cpu_data,
 906                                       struct vcpu_io_intercept *out)
 907 {
 908         struct vmcb *vmcb = &cpu_data->vmcb;
 909         u64 exitinfo = vmcb->exitinfo1;
 910
 911         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 912         out->port = (exitinfo >> 16) & 0xFFFF;
 913         out->size = (exitinfo >> 4) & 0x7;
 914         out->in = !!(exitinfo & 0x1);
 915         out->inst_len = vmcb->exitinfo2 - vmcb->rip;
 916         out->rep_or_str = !!(exitinfo & 0x0c);
 917 }
 918
 919 void vcpu_handle_exit(struct registers *guest_regs, struct per_cpu *cpu_data)
 920 {
 921         struct vmcb *vmcb = &cpu_data->vmcb;
 922         struct vcpu_execution_state x_state;
 923         struct vcpu_pf_intercept pf;
 924         struct vcpu_io_intercept io;
 925         bool res = false;
 926         int sipi_vector;
 927
 928         /* Restore GS value expected by per_cpu data accessors */
 929         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 930
 931         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 932         /*
 933          * All guest state is marked unmodified; individual handlers must clear
 934          * the bits as needed.
 935          */
 936         vmcb->clean_bits = 0xffffffff;
 937
 938         switch (vmcb->exitcode) {
 939         case VMEXIT_INVALID:
 940                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 941                              vmcb->exitcode);
 942                 break;
 943         case VMEXIT_NMI:
 944                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 945                 /* Temporarily enable GIF to consume pending NMI */
 946                 asm volatile("stgi; clgi" : : : "memory");
 947                 sipi_vector = x86_handle_events(cpu_data);
 948                 if (sipi_vector >= 0) {
 949                         printk("CPU %d received SIPI, vector %x\n",
 950                                cpu_data->cpu_id, sipi_vector);
 951                         svm_vcpu_reset(cpu_data, sipi_vector);
 952                         vcpu_reset(guest_regs);
 953                 }
 954                 iommu_check_pending_faults(cpu_data);
 955                 return;
 956         case VMEXIT_CPUID:
 957                 /* FIXME: We are not intercepting CPUID now */
 958                 return;
 959         case VMEXIT_VMMCALL:
 960                 vcpu_vendor_get_execution_state(&x_state);
 961                 vcpu_handle_hypercall(guest_regs, &x_state);
 962                 return;
 963         case VMEXIT_CR0_SEL_WRITE:
 964                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 965                 if (svm_handle_cr(guest_regs, cpu_data))
 966                         return;
 967                 break;
 968         case VMEXIT_MSR:
 969                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 970                 if (!vmcb->exitinfo1)
 971                         res = vcpu_handle_msr_read(guest_regs);
 972                 else
 973                         res = svm_handle_msr_write(guest_regs, cpu_data);
 974                 if (res)
 975                         return;
 976                 break;
 977         case VMEXIT_NPF:
 978                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
 979                      vmcb->exitinfo2 >= XAPIC_BASE &&
 980                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
 981                         /* APIC access in non-AVIC mode */
 982                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
 983                         if (svm_handle_apic_access(guest_regs, cpu_data))
 984                                 return;
 985                 } else {
 986                         /* General MMIO (IOAPIC, PCI etc) */
 987                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
 988                         svm_get_vcpu_pf_intercept(cpu_data, &pf);
 989                         if (vcpu_handle_pt_violation(guest_regs, &pf))
 990                                 return;
 991                 }
 992
 993                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
 994                              "error code is %x\n", vmcb->exitinfo2,
 995                              vmcb->exitinfo1 & 0xf);
 996                 break;
 997         case VMEXIT_XSETBV:
 998                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XSETBV]++;
 999                 if ((guest_regs->rax & X86_XCR0_FP) &&
1000                     (guest_regs->rax & ~cpuid_eax(0x0d)) == 0 &&
1001                     guest_regs->rcx == 0 && guest_regs->rdx == 0) {
1002                         vcpu_skip_emulated_instruction(X86_INST_LEN_XSETBV);
1003                         asm volatile(
1004                                 "xsetbv"
1005                                 : /* no output */
1006                                 : "a" (guest_regs->rax), "c" (0), "d" (0));
1007                         return;
1008                 }
1009                 panic_printk("FATAL: Invalid xsetbv parameters: "
1010                              "xcr[%d] = %x:%x\n", guest_regs->rcx,
1011                              guest_regs->rdx, guest_regs->rax);
1012                 break;
1013         case VMEXIT_IOIO:
1014                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
1015                 svm_get_vcpu_io_intercept(cpu_data, &io);
1016                 if (vcpu_handle_io_access(guest_regs, &io))
1017                         return;
1018                 break;
1019         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
1020         default:
1021                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
1022                              "exitinfo1 %p exitinfo2 %p\n",
1023                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
1024         }
1025         dump_guest_regs(guest_regs, vmcb);
1026         panic_park();
1027 }
1028
1029 void vcpu_park(struct per_cpu *cpu_data)
1030 {
1031         struct vmcb *vmcb = &cpu_data->vmcb;
1032
1033         svm_vcpu_reset(cpu_data, APIC_BSP_PSEUDO_SIPI);
1034         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
1035         vmcb->n_cr3 = paging_hvirt2phys(parked_mode_npt);
1036
1037         vcpu_tlb_flush();
1038 }
1039
1040 void vcpu_nmi_handler(void)
1041 {
1042 }
1043
1044 void vcpu_tlb_flush(void)
1045 {
1046         struct per_cpu *cpu_data = this_cpu_data();
1047         struct vmcb *vmcb = &cpu_data->vmcb;
1048
1049         if (has_flush_by_asid)
1050                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1051         else
1052                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1053 }
1054
1055 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1056                               unsigned long pc, unsigned int *size)
1057 {
1058         struct per_cpu *cpu_data = this_cpu_data();
1059         struct vmcb *vmcb = &cpu_data->vmcb;
1060         unsigned long start;
1061
1062         if (has_assists) {
1063                 if (!*size)
1064                         return NULL;
1065                 start = vmcb->rip - pc;
1066                 if (start < vmcb->bytes_fetched) {
1067                         *size = vmcb->bytes_fetched - start;
1068                         return &vmcb->guest_bytes[start];
1069                 } else {
1070                         return NULL;
1071                 }
1072         } else {
1073                 return vcpu_map_inst(pg_structs, pc, size);
1074         }
1075 }
1076
1077 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1078                                     struct vcpu_io_bitmap *iobm)
1079 {
1080         iobm->data = cell->svm.iopm;
1081         iobm->size = sizeof(cell->svm.iopm);
1082 }
1083
1084 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1085 {
1086         struct per_cpu *cpu_data = this_cpu_data();
1087
1088         x_state->efer = cpu_data->vmcb.efer;
1089         x_state->rflags = cpu_data->vmcb.rflags;
1090         x_state->cs = cpu_data->vmcb.cs.selector;
1091         x_state->rip = cpu_data->vmcb.rip;
1092 }
1093
1094 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1095 void enable_irq(void)
1096 {
1097         asm volatile("stgi; sti" : : : "memory");
1098 }
1099
1100 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1101 void disable_irq(void)
1102 {
1103         asm volatile("cli; clgi" : : : "memory");
1104 }