2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) ARM Limited, 2014
7 * Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #include <jailhouse/entry.h>
14 #include <jailhouse/mmio.h>
15 #include <jailhouse/paging.h>
16 #include <jailhouse/printk.h>
17 #include <jailhouse/string.h>
18 #include <asm/gic_common.h>
19 #include <asm/irqchip.h>
20 #include <asm/platform.h>
21 #include <asm/setup.h>
22 #include <asm/sysregs.h>
25 #define AMBA_DEVICE 0xb105f00d
28 unsigned long gicd_size;
31 * The init function must be called after the MMU setup, and whilst in the
32 * per-cpu setup, which means that a bool must be set by the master CPU
34 static bool irqchip_is_init;
35 static struct irqchip_ops irqchip;
37 bool spi_in_cell(struct cell *cell, unsigned int spi)
39 /* FIXME: Change the configuration to a bitmask range */
45 spi_mask = cell->arch.spis >> 32;
47 spi_mask = cell->arch.spis;
49 return spi_mask & (1 << (spi & 31));
52 static int irqchip_init_pending(struct per_cpu *cpu_data)
54 struct pending_irq *pend_array;
56 if (cpu_data->pending_irqs == NULL) {
57 cpu_data->pending_irqs = pend_array = page_alloc(&mem_pool, 1);
58 if (pend_array == NULL)
61 pend_array = cpu_data->pending_irqs;
64 memset(pend_array, 0, PAGE_SIZE);
66 cpu_data->pending_irqs = pend_array;
67 cpu_data->first_pending = NULL;
73 * Find the first available pending struct for insertion. The `prev' pointer is
74 * set to the previous pending interrupt, if any, to help inserting the new one
76 * Returns NULL when no slot is available
78 static struct pending_irq* get_pending_slot(struct per_cpu *cpu_data,
79 struct pending_irq **prev)
82 struct pending_irq *pending = cpu_data->first_pending;
86 for (i = 0; i < MAX_PENDING_IRQS; i++) {
87 pending_idx = pending - cpu_data->pending_irqs;
88 if (pending == NULL || i < pending_idx)
89 return cpu_data->pending_irqs + i;
92 pending = pending->next;
98 int irqchip_insert_pending(struct per_cpu *cpu_data, struct pending_irq *irq)
100 struct pending_irq *prev = NULL;
101 struct pending_irq *slot;
103 spin_lock(&cpu_data->gic_lock);
105 slot = get_pending_slot(cpu_data, &prev);
107 spin_unlock(&cpu_data->gic_lock);
112 * Don't override the pointers yet, they may be read by the injection
113 * loop. Odds are astronomically low, but hey.
115 memcpy(slot, irq, sizeof(struct pending_irq) - 2 * sizeof(void *));
118 slot->next = prev->next;
121 slot->next = cpu_data->first_pending;
122 cpu_data->first_pending = slot;
125 slot->next->prev = slot;
127 spin_unlock(&cpu_data->gic_lock);
132 void irqchip_set_pending(struct per_cpu *cpu_data, u32 irq_id, bool try_inject)
134 struct pending_irq pending;
136 pending.virt_id = irq_id;
138 if (try_inject && irqchip.inject_irq(cpu_data, &pending) == 0)
141 irqchip_insert_pending(cpu_data, &pending);
145 * Only executed by `irqchip_inject_pending' on a CPU to inject its own stuff.
147 int irqchip_remove_pending(struct per_cpu *cpu_data, struct pending_irq *irq)
149 spin_lock(&cpu_data->gic_lock);
151 if (cpu_data->first_pending == irq)
152 cpu_data->first_pending = irq->next;
154 irq->prev->next = irq->next;
156 irq->next->prev = irq->prev;
158 spin_unlock(&cpu_data->gic_lock);
163 void irqchip_inject_pending(struct per_cpu *cpu_data)
166 struct pending_irq *pending = cpu_data->first_pending;
168 while (pending != NULL) {
169 err = irqchip.inject_irq(cpu_data, pending);
171 /* The list registers are full. */
175 * Removal only changes the pointers, but does not
176 * deallocate anything.
177 * Concurrent accesses are avoided with the spinlock,
178 * but the `next' pointer of the current pending object
179 * may be rewritten by an external insert before or
180 * after this removal, which isn't an issue.
182 irqchip_remove_pending(cpu_data, pending);
184 pending = pending->next;
188 void irqchip_handle_irq(struct per_cpu *cpu_data)
190 irqchip.handle_irq(cpu_data);
193 void irqchip_eoi_irq(u32 irqn, bool deactivate)
195 irqchip.eoi_irq(irqn, deactivate);
198 int irqchip_send_sgi(struct sgi *sgi)
200 return irqchip.send_sgi(sgi);
203 int irqchip_cpu_init(struct per_cpu *cpu_data)
207 err = irqchip_init_pending(cpu_data);
211 if (irqchip.cpu_init)
212 return irqchip.cpu_init(cpu_data);
217 int irqchip_cpu_reset(struct per_cpu *cpu_data)
221 err = irqchip_init_pending(cpu_data);
225 if (irqchip.cpu_reset)
226 return irqchip.cpu_reset(cpu_data, false);
231 void irqchip_cpu_shutdown(struct per_cpu *cpu_data)
234 * The GIC backend must take care of only resetting the hyp interface if
235 * it has been initialised: this function may be executed during the
238 if (irqchip.cpu_reset)
239 irqchip.cpu_reset(cpu_data, true);
242 static const struct jailhouse_irqchip *
243 irqchip_find_config(struct jailhouse_cell_desc *config)
245 const struct jailhouse_irqchip *irq_config =
246 jailhouse_cell_irqchips(config);
248 if (config->num_irqchips)
254 int irqchip_cell_init(struct cell *cell)
256 const struct jailhouse_irqchip *pins = irqchip_find_config(cell->config);
258 cell->arch.spis = (pins ? pins->pin_bitmap : 0);
260 return irqchip.cell_init(cell);
263 void irqchip_cell_exit(struct cell *cell)
265 const struct jailhouse_irqchip *root_pins =
266 irqchip_find_config(root_cell.config);
268 /* might be called by arch_shutdown while rolling back
270 if (!irqchip_is_init)
274 root_cell.arch.spis |= cell->arch.spis & root_pins->pin_bitmap;
276 irqchip.cell_exit(cell);
279 void irqchip_root_cell_shrink(struct cell *cell)
281 root_cell.arch.spis &= ~(cell->arch.spis);
284 /* Only the GIC is implemented */
285 extern struct irqchip_ops gic_irqchip;
287 int irqchip_init(void)
293 /* Only executed on master CPU */
297 /* FIXME: parse device tree */
298 gicd_base = GICD_BASE;
299 gicd_size = GICD_SIZE;
301 if ((err = arch_map_device(gicd_base, gicd_base, gicd_size)) != 0)
304 for (i = 3; i >= 0; i--) {
305 cidr = mmio_read32(gicd_base + GICD_CIDR0 + i * 4);
306 dev_id |= cidr << i * 8;
308 if (dev_id != AMBA_DEVICE)
309 goto err_no_distributor;
311 /* Probe the GIC version */
312 pidr2 = mmio_read32(gicd_base + GICD_PIDR2);
313 switch (GICD_PIDR2_ARCH(pidr2)) {
317 memcpy(&irqchip, &gic_irqchip, sizeof(struct irqchip_ops));
322 err = irqchip.init();
323 irqchip_is_init = true;
329 printk("GIC: no distributor found\n");
330 arch_unmap_device(gicd_base, gicd_size);