hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 static bool has_avic, has_assists, has_flush_by_asid;
  43
  44 static const struct segment invalid_seg;
  45
  46 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  47
  48 /* bit cleared: direct access allowed */
  49 // TODO: convert to whitelist
  50 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  51         [ SVM_MSRPM_0000 ] = {
  52                 [      0/4 ...  0x017/4 ] = 0,
  53                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  54                 [  0x01c/4 ...  0x1ff/4 ] = 0,
  55                 [  0x200/4 ...  0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
  56                 [  0x274/4 ...  0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
  57                 [  0x278/4 ...  0x2fb/4 ] = 0,
  58                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  59                 [  0x300/4 ...  0x7ff/4 ] = 0,
  60                 /* x2APIC MSRs - emulated if not present */
  61                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  62                 [  0x804/4 ...  0x807/4 ] = 0,
  63                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  64                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  65                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  66                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  67                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  68                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  69                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  70                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  71                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  72                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  73                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  74                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  75                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  76                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  77                 [  0x840/4 ... 0x1fff/4 ] = 0,
  78         },
  79         [ SVM_MSRPM_C000 ] = {
  80                 [      0/4 ...  0x07f/4 ] = 0,
  81                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  82                 [  0x084/4 ... 0x1fff/4 ] = 0
  83         },
  84         [ SVM_MSRPM_C001 ] = {
  85                 [      0/4 ... 0x1fff/4 ] = 0,
  86         },
  87         [ SVM_MSRPM_RESV ] = {
  88                 [      0/4 ... 0x1fff/4 ] = 0,
  89         }
  90 };
  91
  92 /* This page is mapped so the code begins at 0x000ffff0 */
  93 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  94         [0xff0] = 0xfa, /* 1: cli */
  95         [0xff1] = 0xf4, /*    hlt */
  96         [0xff2] = 0xeb,
  97         [0xff3] = 0xfc  /*    jmp 1b */
  98 };
  99
 100 static void *parked_mode_npt;
 101
 102 static void *avic_page;
 103
 104 static int svm_check_features(void)
 105 {
 106         /* SVM is available */
 107         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 108                 return trace_error(-ENODEV);
 109
 110         /* Nested paging */
 111         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 112                 return trace_error(-EIO);
 113
 114         /* Decode assists */
 115         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 116                 has_assists = true;
 117
 118         /* AVIC support */
 119         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 120                 has_avic = true;
 121
 122         /* TLB Flush by ASID support */
 123         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 124                 has_flush_by_asid = true;
 125
 126         return 0;
 127 }
 128
 129 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 130                                      const struct desc_table_reg *dtr)
 131 {
 132         svm_segment->base = dtr->base;
 133         svm_segment->limit = dtr->limit & 0xffff;
 134 }
 135
 136 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 137                                          const struct segment *segment)
 138 {
 139         svm_segment->selector = segment->selector;
 140         svm_segment->access_rights = ((segment->access_rights & 0xf000) >> 4) |
 141                 (segment->access_rights & 0x00ff);
 142         svm_segment->limit = segment->limit;
 143         svm_segment->base = segment->base;
 144 }
 145
 146 static void svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 147 {
 148         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 149         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 150 }
 151
 152 static void vmcb_setup(struct per_cpu *cpu_data)
 153 {
 154         struct vmcb *vmcb = &cpu_data->vmcb;
 155
 156         memset(vmcb, 0, sizeof(struct vmcb));
 157
 158         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 159         vmcb->cr3 = cpu_data->linux_cr3;
 160         vmcb->cr4 = cpu_data->linux_cr4;
 161
 162         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 163         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 164         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 165         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 166         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 167         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 168         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 169         set_svm_segment_from_segment(&vmcb->ldtr, &invalid_seg);
 170
 171         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 172         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 173
 174         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 175
 176         vmcb->rflags = 0x02;
 177         /* Indicate success to the caller of arch_entry */
 178         vmcb->rax = 0;
 179         vmcb->rsp = cpu_data->linux_sp +
 180                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 181         vmcb->rip = cpu_data->linux_ip;
 182
 183         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 184         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 185         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 186         vmcb->star = read_msr(MSR_STAR);
 187         vmcb->lstar = read_msr(MSR_LSTAR);
 188         vmcb->cstar = read_msr(MSR_CSTAR);
 189         vmcb->sfmask = read_msr(MSR_SFMASK);
 190         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 191
 192         vmcb->dr6 = 0x00000ff0;
 193         vmcb->dr7 = 0x00000400;
 194
 195         /* Make the hypervisor visible */
 196         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 197
 198         vmcb->g_pat = cpu_data->pat;
 199
 200         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 201         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 202         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 203         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 204         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 205
 206         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 207         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 208
 209         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 210
 211         vmcb->np_enable = 1;
 212         /* No more than one guest owns the CPU */
 213         vmcb->guest_asid = 1;
 214
 215         /* TODO: Setup AVIC */
 216
 217         /* Explicitly mark all of the state as new */
 218         vmcb->clean_bits = 0;
 219
 220         svm_set_cell_config(cpu_data->cell, vmcb);
 221 }
 222
 223 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 224                                      unsigned long gphys,
 225                                      unsigned long flags)
 226 {
 227         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 228                         gphys, flags);
 229 }
 230
 231 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 232 {
 233         /* See APMv2, Section 15.25.5 */
 234         *pte = (next_pt & 0x000ffffffffff000UL) |
 235                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 236 }
 237
 238 int vcpu_vendor_init(void)
 239 {
 240         struct paging_structures parking_pt;
 241         unsigned long vm_cr;
 242         int err, n;
 243
 244         err = svm_check_features();
 245         if (err)
 246                 return err;
 247
 248         vm_cr = read_msr(MSR_VM_CR);
 249         if (vm_cr & VM_CR_SVMDIS)
 250                 /* SVM disabled in BIOS */
 251                 return trace_error(-EPERM);
 252
 253         /* Nested paging is the same as the native one */
 254         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 255         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 256                 npt_paging[n].set_next_pt = npt_set_next_pt;
 257
 258         /* Map guest parking code (shared between cells and CPUs) */
 259         parking_pt.root_paging = npt_paging;
 260         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 261         if (!parked_mode_npt)
 262                 return -ENOMEM;
 263         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 264                             PAGE_SIZE, 0x000ff000,
 265                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 266                             PAGING_NON_COHERENT);
 267         if (err)
 268                 return err;
 269
 270         /* This is always false for AMD now (except in nested SVM);
 271            see Sect. 16.3.1 in APMv2 */
 272         if (using_x2apic) {
 273                 /* allow direct x2APIC access except for ICR writes */
 274                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 275                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 276                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 277         } else {
 278                 if (has_avic) {
 279                         avic_page = page_alloc(&remap_pool, 1);
 280                         if (!avic_page)
 281                                 return trace_error(-ENOMEM);
 282                 }
 283         }
 284
 285         return vcpu_cell_init(&root_cell);
 286 }
 287
 288 int vcpu_vendor_cell_init(struct cell *cell)
 289 {
 290         u64 flags;
 291         int err;
 292
 293         /* allocate iopm (two 4-K pages + 3 bits) */
 294         cell->svm.iopm = page_alloc(&mem_pool, 3);
 295         if (!cell->svm.iopm)
 296                 return -ENOMEM;
 297
 298         /* build root NPT of cell */
 299         cell->svm.npt_structs.root_paging = npt_paging;
 300         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 301         if (!cell->svm.npt_structs.root_table)
 302                 return -ENOMEM;
 303
 304         if (!has_avic) {
 305                 /*
 306                  * Map xAPIC as is; reads are passed, writes are trapped.
 307                  */
 308                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 309                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 310                                     PAGE_SIZE, XAPIC_BASE,
 311                                     flags,
 312                                     PAGING_NON_COHERENT);
 313         } else {
 314                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 315                 err = paging_create(&cell->svm.npt_structs,
 316                                     paging_hvirt2phys(avic_page),
 317                                     PAGE_SIZE, XAPIC_BASE,
 318                                     flags,
 319                                     PAGING_NON_COHERENT);
 320         }
 321
 322         return err;
 323 }
 324
 325 int vcpu_map_memory_region(struct cell *cell,
 326                            const struct jailhouse_memory *mem)
 327 {
 328         u64 phys_start = mem->phys_start;
 329         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 330
 331         if (mem->flags & JAILHOUSE_MEM_READ)
 332                 flags |= PAGE_FLAG_PRESENT;
 333         if (mem->flags & JAILHOUSE_MEM_WRITE)
 334                 flags |= PAGE_FLAG_RW;
 335         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 336                 flags |= PAGE_FLAG_NOEXECUTE;
 337         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 338                 phys_start = paging_hvirt2phys(&cell->comm_page);
 339
 340         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 341                              mem->virt_start, flags, PAGING_NON_COHERENT);
 342 }
 343
 344 int vcpu_unmap_memory_region(struct cell *cell,
 345                              const struct jailhouse_memory *mem)
 346 {
 347         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 348                               mem->size, PAGING_NON_COHERENT);
 349 }
 350
 351 void vcpu_vendor_cell_exit(struct cell *cell)
 352 {
 353         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 354                        PAGING_NON_COHERENT);
 355         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 356 }
 357
 358 int vcpu_init(struct per_cpu *cpu_data)
 359 {
 360         unsigned long efer;
 361         int err;
 362
 363         err = svm_check_features();
 364         if (err)
 365                 return err;
 366
 367         efer = read_msr(MSR_EFER);
 368         if (efer & EFER_SVME)
 369                 return trace_error(-EBUSY);
 370
 371         efer |= EFER_SVME;
 372         write_msr(MSR_EFER, efer);
 373
 374         cpu_data->svm_state = SVMON;
 375
 376         vmcb_setup(cpu_data);
 377
 378         /*
 379          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 380          * set the values of reserved bits to the values found during the
 381          * previous CR0 read."
 382          * But we want to avoid surprises with new features unknown to us but
 383          * set by Linux. So check if any assumed revered bit was set and bail
 384          * out if so.
 385          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 386          */
 387         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 388                 return -EIO;
 389
 390         /* bring CR0 and CR4 into well-defined states */
 391         write_cr0(X86_CR0_HOST_STATE);
 392         write_cr4(X86_CR4_HOST_STATE);
 393
 394         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 395
 396         return 0;
 397 }
 398
 399 void vcpu_exit(struct per_cpu *cpu_data)
 400 {
 401         unsigned long efer;
 402
 403         if (cpu_data->svm_state == SVMOFF)
 404                 return;
 405
 406         cpu_data->svm_state = SVMOFF;
 407
 408         /* We are leaving - set the GIF */
 409         asm volatile ("stgi" : : : "memory");
 410
 411         efer = read_msr(MSR_EFER);
 412         efer &= ~EFER_SVME;
 413         write_msr(MSR_EFER, efer);
 414
 415         write_msr(MSR_VM_HSAVE_PA, 0);
 416 }
 417
 418 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 419 {
 420         unsigned long vmcb_pa, host_stack;
 421
 422         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 423         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 424
 425         /* We enter Linux at the point arch_entry would return to as well.
 426          * rax is cleared to signal success to the caller. */
 427         asm volatile(
 428                 "clgi\n\t"
 429                 "mov (%%rdi),%%r15\n\t"
 430                 "mov 0x8(%%rdi),%%r14\n\t"
 431                 "mov 0x10(%%rdi),%%r13\n\t"
 432                 "mov 0x18(%%rdi),%%r12\n\t"
 433                 "mov 0x20(%%rdi),%%rbx\n\t"
 434                 "mov 0x28(%%rdi),%%rbp\n\t"
 435                 "mov %2,%%rsp\n\t"
 436                 "jmp svm_vmentry"
 437                 : /* no output */
 438                 : "D" (cpu_data->linux_reg), "a" (vmcb_pa), "m" (host_stack));
 439         __builtin_unreachable();
 440 }
 441
 442 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
 443 {
 444         struct per_cpu *cpu_data = this_cpu_data();
 445         struct vmcb *vmcb = &cpu_data->vmcb;
 446         unsigned long *stack = (unsigned long *)vmcb->rsp;
 447         unsigned long linux_ip = vmcb->rip;
 448
 449         cpu_data->linux_cr0 = vmcb->cr0;
 450         cpu_data->linux_cr3 = vmcb->cr3;
 451
 452         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 453         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 454         cpu_data->linux_idtr.base = vmcb->idtr.base;
 455         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 456
 457         cpu_data->linux_cs.selector = vmcb->cs.selector;
 458
 459         cpu_data->linux_tss.selector = vmcb->tr.selector;
 460
 461         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 462         cpu_data->linux_gs.base = vmcb->gs.base;
 463
 464         cpu_data->linux_ds.selector = vmcb->ds.selector;
 465         cpu_data->linux_es.selector = vmcb->es.selector;
 466         cpu_data->linux_fs.selector = vmcb->fs.selector;
 467         cpu_data->linux_gs.selector = vmcb->gs.selector;
 468
 469         arch_cpu_restore(cpu_data, 0);
 470
 471         stack--;
 472         *stack = linux_ip;
 473
 474         asm volatile (
 475                 "mov %%rbx,%%rsp\n\t"
 476                 "pop %%r15\n\t"
 477                 "pop %%r14\n\t"
 478                 "pop %%r13\n\t"
 479                 "pop %%r12\n\t"
 480                 "pop %%r11\n\t"
 481                 "pop %%r10\n\t"
 482                 "pop %%r9\n\t"
 483                 "pop %%r8\n\t"
 484                 "pop %%rdi\n\t"
 485                 "pop %%rsi\n\t"
 486                 "pop %%rbp\n\t"
 487                 "add $8,%%rsp\n\t"
 488                 "pop %%rbx\n\t"
 489                 "pop %%rdx\n\t"
 490                 "pop %%rcx\n\t"
 491                 "mov %%rax,%%rsp\n\t"
 492                 "xor %%rax,%%rax\n\t"
 493                 "ret"
 494                 : : "a" (stack), "b" (&cpu_data->guest_regs));
 495         __builtin_unreachable();
 496 }
 497
 498 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 499 {
 500         static const struct svm_segment dataseg_reset_state = {
 501                 .selector = 0,
 502                 .base = 0,
 503                 .limit = 0xffff,
 504                 .access_rights = 0x0093,
 505         };
 506         static const struct svm_segment dtr_reset_state = {
 507                 .selector = 0,
 508                 .base = 0,
 509                 .limit = 0xffff,
 510                 .access_rights = 0,
 511         };
 512         struct vmcb *vmcb = &cpu_data->vmcb;
 513         unsigned long val;
 514
 515         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 516         vmcb->cr3 = 0;
 517         vmcb->cr4 = 0;
 518
 519         vmcb->rflags = 0x02;
 520
 521         val = 0;
 522         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 523                 val = 0xfff0;
 524                 sipi_vector = 0xf0;
 525         }
 526         vmcb->rip = val;
 527         vmcb->rsp = 0;
 528
 529         vmcb->cs.selector = sipi_vector << 8;
 530         vmcb->cs.base = sipi_vector << 12;
 531         vmcb->cs.limit = 0xffff;
 532         vmcb->cs.access_rights = 0x009b;
 533
 534         vmcb->ds = dataseg_reset_state;
 535         vmcb->es = dataseg_reset_state;
 536         vmcb->fs = dataseg_reset_state;
 537         vmcb->gs = dataseg_reset_state;
 538         vmcb->ss = dataseg_reset_state;
 539
 540         vmcb->tr.selector = 0;
 541         vmcb->tr.base = 0;
 542         vmcb->tr.limit = 0xffff;
 543         vmcb->tr.access_rights = 0x008b;
 544
 545         vmcb->ldtr.selector = 0;
 546         vmcb->ldtr.base = 0;
 547         vmcb->ldtr.limit = 0xffff;
 548         vmcb->ldtr.access_rights = 0x0082;
 549
 550         vmcb->gdtr = dtr_reset_state;
 551         vmcb->idtr = dtr_reset_state;
 552
 553         vmcb->efer = EFER_SVME;
 554
 555         /* These MSRs are undefined on reset */
 556         vmcb->star = 0;
 557         vmcb->lstar = 0;
 558         vmcb->cstar = 0;
 559         vmcb->sfmask = 0;
 560         vmcb->sysenter_cs = 0;
 561         vmcb->sysenter_eip = 0;
 562         vmcb->sysenter_esp = 0;
 563         vmcb->kerngsbase = 0;
 564
 565         vmcb->dr7 = 0x00000400;
 566
 567         /* Almost all of the guest state changed */
 568         vmcb->clean_bits = 0;
 569
 570         svm_set_cell_config(cpu_data->cell, vmcb);
 571 }
 572
 573 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 574 {
 575         this_cpu_data()->vmcb.rip += inst_len;
 576 }
 577
 578 static void update_efer(struct vmcb *vmcb)
 579 {
 580         unsigned long efer = vmcb->efer;
 581
 582         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 583                 return;
 584
 585         efer |= EFER_LMA;
 586
 587         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 588         if ((vmcb->efer ^ efer) & EFER_LMA)
 589                 vcpu_tlb_flush();
 590
 591         vmcb->efer = efer;
 592         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 593 }
 594
 595 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 596 {
 597         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 598
 599         if (vmcb->efer & EFER_LMA) {
 600                 pg_structs->root_paging = x86_64_paging;
 601                 pg_structs->root_table_gphys =
 602                         vmcb->cr3 & 0x000ffffffffff000UL;
 603         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 604                    !(vmcb->cr4 & X86_CR4_PAE)) {
 605                 pg_structs->root_paging = i386_paging;
 606                 pg_structs->root_table_gphys =
 607                         vmcb->cr3 & 0xfffff000UL;
 608         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 609                 /*
 610                  * Can be in non-paged protected mode as well, but
 611                  * the translation mechanism will stay the same ayway.
 612                  */
 613                 pg_structs->root_paging = realmode_paging;
 614                 /*
 615                  * This will make paging_get_guest_pages map the page
 616                  * that also contains the bootstrap code and, thus, is
 617                  * always present in a cell.
 618                  */
 619                 pg_structs->root_table_gphys = 0xff000;
 620         } else {
 621                 printk("FATAL: Unsupported paging mode\n");
 622                 return false;
 623         }
 624         return true;
 625 }
 626
 627 void vcpu_vendor_set_guest_pat(unsigned long val)
 628 {
 629         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 630
 631         vmcb->g_pat = val;
 632         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 633 }
 634
 635 struct parse_context {
 636         unsigned int remaining;
 637         unsigned int size;
 638         unsigned long cs_base;
 639         const u8 *inst;
 640 };
 641
 642 static bool ctx_advance(struct parse_context *ctx,
 643                         unsigned long *pc,
 644                         struct guest_paging_structures *pg_structs)
 645 {
 646         if (!ctx->size) {
 647                 ctx->size = ctx->remaining;
 648                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 649                                           &ctx->size);
 650                 if (!ctx->inst)
 651                         return false;
 652                 ctx->remaining -= ctx->size;
 653                 *pc += ctx->size;
 654         }
 655         return true;
 656 }
 657
 658 static bool svm_parse_mov_to_cr(struct vmcb *vmcb, unsigned long pc,
 659                                 unsigned char reg, unsigned long *gpr)
 660 {
 661         struct guest_paging_structures pg_structs;
 662         struct parse_context ctx = {};
 663         /* No prefixes are supported yet */
 664         u8 opcodes[] = {0x0f, 0x22}, modrm;
 665         int n;
 666
 667         ctx.remaining = ARRAY_SIZE(opcodes);
 668         if (!vcpu_get_guest_paging_structs(&pg_structs))
 669                 return false;
 670         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 671
 672         if (!ctx_advance(&ctx, &pc, &pg_structs))
 673                 return false;
 674
 675         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++)
 676                 if (*(ctx.inst) != opcodes[n] ||
 677                     !ctx_advance(&ctx, &pc, &pg_structs))
 678                         return false;
 679
 680         if (!ctx_advance(&ctx, &pc, &pg_structs))
 681                 return false;
 682
 683         modrm = *(ctx.inst);
 684
 685         if (((modrm & 0x38) >> 3) != reg)
 686                 return false;
 687
 688         if (gpr)
 689                 *gpr = (modrm & 0x7);
 690
 691         return true;
 692 }
 693
 694 /*
 695  * XXX: The only visible reason to have this function (vmx.c consistency
 696  * aside) is to prevent cells from setting invalid CD+NW combinations that
 697  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 698  * altogether?
 699  */
 700 static bool svm_handle_cr(struct per_cpu *cpu_data)
 701 {
 702         struct vmcb *vmcb = &cpu_data->vmcb;
 703         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 704         unsigned long reg = -1, val, bits;
 705
 706         if (has_assists) {
 707                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 708                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 709                         return false;
 710                 }
 711                 reg = vmcb->exitinfo1 & 0x07;
 712         } else {
 713                 if (!svm_parse_mov_to_cr(vmcb, vmcb->rip, 0, &reg)) {
 714                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 715                         return false;
 716                 }
 717         };
 718
 719         if (reg == 4)
 720                 val = vmcb->rsp;
 721         else
 722                 val = cpu_data->guest_regs.by_index[15 - reg];
 723
 724         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 725         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 726         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 727         if ((val ^ vmcb->cr0) & bits)
 728                 vcpu_tlb_flush();
 729         /* TODO: better check for #GP reasons */
 730         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 731         if (val & X86_CR0_PG)
 732                 update_efer(vmcb);
 733         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 734
 735         return true;
 736 }
 737
 738 static bool svm_handle_msr_write(struct per_cpu *cpu_data)
 739 {
 740         struct vmcb *vmcb = &cpu_data->vmcb;
 741         unsigned long efer;
 742
 743         if (cpu_data->guest_regs.rcx == MSR_EFER) {
 744                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 745                 efer = get_wrmsr_value(&cpu_data->guest_regs) | EFER_SVME;
 746                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 747                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 748                         vcpu_tlb_flush();
 749                 vmcb->efer = efer;
 750                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 751                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 752                 return true;
 753         }
 754
 755         return vcpu_handle_msr_write();
 756 }
 757
 758 /*
 759  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 760  * be treated separately in svm_handle_avic_access().
 761  */
 762 static bool svm_handle_apic_access(struct vmcb *vmcb)
 763 {
 764         struct guest_paging_structures pg_structs;
 765         unsigned int inst_len, offset;
 766         bool is_write;
 767
 768         /* The caller is responsible for sanity checks */
 769         is_write = !!(vmcb->exitinfo1 & 0x2);
 770         offset = vmcb->exitinfo2 - XAPIC_BASE;
 771
 772         if (offset & 0x00f)
 773                 goto out_err;
 774
 775         if (!vcpu_get_guest_paging_structs(&pg_structs))
 776                 goto out_err;
 777
 778         inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
 779                                     is_write);
 780         if (!inst_len)
 781                 goto out_err;
 782
 783         vcpu_skip_emulated_instruction(inst_len);
 784         return true;
 785
 786 out_err:
 787         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 788                      offset, is_write);
 789         return false;
 790 }
 791
 792 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
 793 {
 794         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 795                      vmcb->rsp, vmcb->rflags);
 796         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 797                      guest_regs->rbx, guest_regs->rcx);
 798         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 799                      guest_regs->rsi, guest_regs->rdi);
 800         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 801                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 802                      !!(vmcb->efer & EFER_LMA));
 803         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 804                      vmcb->cr3, vmcb->cr4);
 805         panic_printk("EFER: %p\n", vmcb->efer);
 806 }
 807
 808 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
 809 {
 810         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 811         u64 exitinfo = vmcb->exitinfo1;
 812
 813         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 814         io->port = (exitinfo >> 16) & 0xFFFF;
 815         io->size = (exitinfo >> 4) & 0x7;
 816         io->in = !!(exitinfo & 0x1);
 817         io->inst_len = vmcb->exitinfo2 - vmcb->rip;
 818         io->rep_or_str = !!(exitinfo & 0x0c);
 819 }
 820
 821 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
 822 {
 823         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 824
 825         mmio->phys_addr = vmcb->exitinfo2;
 826         mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
 827 }
 828
 829 void vcpu_handle_exit(struct per_cpu *cpu_data)
 830 {
 831         struct vmcb *vmcb = &cpu_data->vmcb;
 832         bool res = false;
 833         int sipi_vector;
 834
 835         /* Restore GS value expected by per_cpu data accessors */
 836         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 837
 838         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 839         /*
 840          * All guest state is marked unmodified; individual handlers must clear
 841          * the bits as needed.
 842          */
 843         vmcb->clean_bits = 0xffffffff;
 844
 845         switch (vmcb->exitcode) {
 846         case VMEXIT_INVALID:
 847                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 848                              vmcb->exitcode);
 849                 break;
 850         case VMEXIT_NMI:
 851                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 852                 /* Temporarily enable GIF to consume pending NMI */
 853                 asm volatile("stgi; clgi" : : : "memory");
 854                 sipi_vector = x86_handle_events(cpu_data);
 855                 if (sipi_vector >= 0) {
 856                         printk("CPU %d received SIPI, vector %x\n",
 857                                cpu_data->cpu_id, sipi_vector);
 858                         svm_vcpu_reset(cpu_data, sipi_vector);
 859                         vcpu_reset();
 860                 }
 861                 iommu_check_pending_faults(cpu_data);
 862                 return;
 863         case VMEXIT_VMMCALL:
 864                 vcpu_handle_hypercall();
 865                 return;
 866         case VMEXIT_CR0_SEL_WRITE:
 867                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 868                 if (svm_handle_cr(cpu_data))
 869                         return;
 870                 break;
 871         case VMEXIT_MSR:
 872                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 873                 if (!vmcb->exitinfo1)
 874                         res = vcpu_handle_msr_read();
 875                 else
 876                         res = svm_handle_msr_write(cpu_data);
 877                 if (res)
 878                         return;
 879                 break;
 880         case VMEXIT_NPF:
 881                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
 882                      vmcb->exitinfo2 >= XAPIC_BASE &&
 883                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
 884                         /* APIC access in non-AVIC mode */
 885                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
 886                         if (svm_handle_apic_access(vmcb))
 887                                 return;
 888                 } else {
 889                         /* General MMIO (IOAPIC, PCI etc) */
 890                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
 891                         if (vcpu_handle_mmio_access())
 892                                 return;
 893                 }
 894
 895                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
 896                              "error code is %x\n", vmcb->exitinfo2,
 897                              vmcb->exitinfo1 & 0xf);
 898                 break;
 899         case VMEXIT_XSETBV:
 900                 if (vcpu_handle_xsetbv())
 901                         return;
 902                 break;
 903         case VMEXIT_IOIO:
 904                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
 905                 if (vcpu_handle_io_access())
 906                         return;
 907                 break;
 908         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
 909         default:
 910                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
 911                              "exitinfo1 %p exitinfo2 %p\n",
 912                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
 913         }
 914         dump_guest_regs(&cpu_data->guest_regs, vmcb);
 915         panic_park();
 916 }
 917
 918 void vcpu_park(void)
 919 {
 920         svm_vcpu_reset(this_cpu_data(), APIC_BSP_PSEUDO_SIPI);
 921         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
 922         this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
 923
 924         vcpu_tlb_flush();
 925 }
 926
 927 void vcpu_nmi_handler(void)
 928 {
 929 }
 930
 931 void vcpu_tlb_flush(void)
 932 {
 933         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 934
 935         if (has_flush_by_asid)
 936                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
 937         else
 938                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
 939 }
 940
 941 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
 942                               unsigned long pc, unsigned int *size)
 943 {
 944         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 945         unsigned long start;
 946
 947         if (has_assists) {
 948                 if (!*size)
 949                         return NULL;
 950                 start = vmcb->rip - pc;
 951                 if (start < vmcb->bytes_fetched) {
 952                         *size = vmcb->bytes_fetched - start;
 953                         return &vmcb->guest_bytes[start];
 954                 } else {
 955                         return NULL;
 956                 }
 957         } else {
 958                 return vcpu_map_inst(pg_structs, pc, size);
 959         }
 960 }
 961
 962 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
 963                                     struct vcpu_io_bitmap *iobm)
 964 {
 965         iobm->data = cell->svm.iopm;
 966         iobm->size = sizeof(cell->svm.iopm);
 967 }
 968
 969 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
 970 {
 971         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 972
 973         x_state->efer = vmcb->efer;
 974         x_state->rflags = vmcb->rflags;
 975         x_state->cs = vmcb->cs.selector;
 976         x_state->rip = vmcb->rip;
 977 }
 978
 979 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
 980 void enable_irq(void)
 981 {
 982         asm volatile("stgi; sti" : : : "memory");
 983 }
 984
 985 /* Jailhouse runs with GIF cleared, so we need to restore this state */
 986 void disable_irq(void)
 987 {
 988         asm volatile("cli; clgi" : : : "memory");
 989 }