hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 static bool has_avic, has_assists, has_flush_by_asid;
  43
  44 static const struct segment invalid_seg;
  45
  46 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  47
  48 /* bit cleared: direct access allowed */
  49 // TODO: convert to whitelist
  50 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  51         [ SVM_MSRPM_0000 ] = {
  52                 [      0/4 ...  0x017/4 ] = 0,
  53                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  54                 [  0x01c/4 ...  0x1ff/4 ] = 0,
  55                 [  0x200/4 ...  0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
  56                 [  0x274/4 ...  0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
  57                 [  0x278/4 ...  0x2fb/4 ] = 0,
  58                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  59                 [  0x300/4 ...  0x7ff/4 ] = 0,
  60                 /* x2APIC MSRs - emulated if not present */
  61                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  62                 [  0x804/4 ...  0x807/4 ] = 0,
  63                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  64                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  65                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  66                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  67                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  68                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  69                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  70                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  71                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  72                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  73                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  74                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  75                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  76                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  77                 [  0x840/4 ... 0x1fff/4 ] = 0,
  78         },
  79         [ SVM_MSRPM_C000 ] = {
  80                 [      0/4 ...  0x07f/4 ] = 0,
  81                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  82                 [  0x084/4 ... 0x1fff/4 ] = 0
  83         },
  84         [ SVM_MSRPM_C001 ] = {
  85                 [      0/4 ... 0x1fff/4 ] = 0,
  86         },
  87         [ SVM_MSRPM_RESV ] = {
  88                 [      0/4 ... 0x1fff/4 ] = 0,
  89         }
  90 };
  91
  92 /* This page is mapped so the code begins at 0x000ffff0 */
  93 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  94         [0xff0] = 0xfa, /* 1: cli */
  95         [0xff1] = 0xf4, /*    hlt */
  96         [0xff2] = 0xeb,
  97         [0xff3] = 0xfc  /*    jmp 1b */
  98 };
  99
 100 static void *parked_mode_npt;
 101
 102 static void *avic_page;
 103
 104 static int svm_check_features(void)
 105 {
 106         /* SVM is available */
 107         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 108                 return trace_error(-ENODEV);
 109
 110         /* Nested paging */
 111         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 112                 return trace_error(-EIO);
 113
 114         /* Decode assists */
 115         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 116                 has_assists = true;
 117
 118         /* AVIC support */
 119         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 120                 has_avic = true;
 121
 122         /* TLB Flush by ASID support */
 123         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 124                 has_flush_by_asid = true;
 125
 126         return 0;
 127 }
 128
 129 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 130                                      const struct desc_table_reg *dtr)
 131 {
 132         svm_segment->base = dtr->base;
 133         svm_segment->limit = dtr->limit & 0xffff;
 134 }
 135
 136 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 137                                          const struct segment *segment)
 138 {
 139         svm_segment->selector = segment->selector;
 140         svm_segment->access_rights = ((segment->access_rights & 0xf000) >> 4) |
 141                 (segment->access_rights & 0x00ff);
 142         svm_segment->limit = segment->limit;
 143         svm_segment->base = segment->base;
 144 }
 145
 146 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 147 {
 148         /* No real need for this function; used for consistency with vmx.c */
 149         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 150         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 151
 152         return true;
 153 }
 154
 155 static int vmcb_setup(struct per_cpu *cpu_data)
 156 {
 157         struct vmcb *vmcb = &cpu_data->vmcb;
 158
 159         memset(vmcb, 0, sizeof(struct vmcb));
 160
 161         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 162         vmcb->cr3 = cpu_data->linux_cr3;
 163         vmcb->cr4 = cpu_data->linux_cr4;
 164
 165         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 166         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 167         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 168         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 169         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 170         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 171         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 172         set_svm_segment_from_segment(&vmcb->ldtr, &invalid_seg);
 173
 174         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 175         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 176
 177         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 178
 179         vmcb->rflags = 0x02;
 180         /* Indicate success to the caller of arch_entry */
 181         vmcb->rax = 0;
 182         vmcb->rsp = cpu_data->linux_sp +
 183                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 184         vmcb->rip = cpu_data->linux_ip;
 185
 186         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 187         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 188         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 189         vmcb->star = read_msr(MSR_STAR);
 190         vmcb->lstar = read_msr(MSR_LSTAR);
 191         vmcb->cstar = read_msr(MSR_CSTAR);
 192         vmcb->sfmask = read_msr(MSR_SFMASK);
 193         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 194
 195         vmcb->dr6 = 0x00000ff0;
 196         vmcb->dr7 = 0x00000400;
 197
 198         /* Make the hypervisor visible */
 199         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 200
 201         vmcb->g_pat = cpu_data->pat;
 202
 203         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 204         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 205         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 206         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 207         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 208
 209         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 210         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 211
 212         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 213
 214         vmcb->np_enable = 1;
 215         /* No more than one guest owns the CPU */
 216         vmcb->guest_asid = 1;
 217
 218         /* TODO: Setup AVIC */
 219
 220         /* Explicitly mark all of the state as new */
 221         vmcb->clean_bits = 0;
 222
 223         return svm_set_cell_config(cpu_data->cell, vmcb);
 224 }
 225
 226 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 227                                      unsigned long gphys,
 228                                      unsigned long flags)
 229 {
 230         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 231                         gphys, flags);
 232 }
 233
 234 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 235 {
 236         /* See APMv2, Section 15.25.5 */
 237         *pte = (next_pt & 0x000ffffffffff000UL) |
 238                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 239 }
 240
 241 int vcpu_vendor_init(void)
 242 {
 243         struct paging_structures parking_pt;
 244         unsigned long vm_cr;
 245         int err, n;
 246
 247         err = svm_check_features();
 248         if (err)
 249                 return err;
 250
 251         vm_cr = read_msr(MSR_VM_CR);
 252         if (vm_cr & VM_CR_SVMDIS)
 253                 /* SVM disabled in BIOS */
 254                 return trace_error(-EPERM);
 255
 256         /* Nested paging is the same as the native one */
 257         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 258         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 259                 npt_paging[n].set_next_pt = npt_set_next_pt;
 260
 261         /* Map guest parking code (shared between cells and CPUs) */
 262         parking_pt.root_paging = npt_paging;
 263         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 264         if (!parked_mode_npt)
 265                 return -ENOMEM;
 266         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 267                             PAGE_SIZE, 0x000ff000,
 268                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 269                             PAGING_NON_COHERENT);
 270         if (err)
 271                 return err;
 272
 273         /* This is always false for AMD now (except in nested SVM);
 274            see Sect. 16.3.1 in APMv2 */
 275         if (using_x2apic) {
 276                 /* allow direct x2APIC access except for ICR writes */
 277                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 278                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 279                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 280         } else {
 281                 if (has_avic) {
 282                         avic_page = page_alloc(&remap_pool, 1);
 283                         if (!avic_page)
 284                                 return trace_error(-ENOMEM);
 285                 }
 286         }
 287
 288         return vcpu_cell_init(&root_cell);
 289 }
 290
 291 int vcpu_vendor_cell_init(struct cell *cell)
 292 {
 293         u64 flags;
 294         int err;
 295
 296         /* allocate iopm (two 4-K pages + 3 bits) */
 297         cell->svm.iopm = page_alloc(&mem_pool, 3);
 298         if (!cell->svm.iopm)
 299                 return -ENOMEM;
 300
 301         /* build root NPT of cell */
 302         cell->svm.npt_structs.root_paging = npt_paging;
 303         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 304         if (!cell->svm.npt_structs.root_table)
 305                 return -ENOMEM;
 306
 307         if (!has_avic) {
 308                 /*
 309                  * Map xAPIC as is; reads are passed, writes are trapped.
 310                  */
 311                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 312                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 313                                     PAGE_SIZE, XAPIC_BASE,
 314                                     flags,
 315                                     PAGING_NON_COHERENT);
 316         } else {
 317                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 318                 err = paging_create(&cell->svm.npt_structs,
 319                                     paging_hvirt2phys(avic_page),
 320                                     PAGE_SIZE, XAPIC_BASE,
 321                                     flags,
 322                                     PAGING_NON_COHERENT);
 323         }
 324
 325         return err;
 326 }
 327
 328 int vcpu_map_memory_region(struct cell *cell,
 329                            const struct jailhouse_memory *mem)
 330 {
 331         u64 phys_start = mem->phys_start;
 332         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 333
 334         if (mem->flags & JAILHOUSE_MEM_READ)
 335                 flags |= PAGE_FLAG_PRESENT;
 336         if (mem->flags & JAILHOUSE_MEM_WRITE)
 337                 flags |= PAGE_FLAG_RW;
 338         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 339                 flags |= PAGE_FLAG_NOEXECUTE;
 340         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 341                 phys_start = paging_hvirt2phys(&cell->comm_page);
 342
 343         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 344                              mem->virt_start, flags, PAGING_NON_COHERENT);
 345 }
 346
 347 int vcpu_unmap_memory_region(struct cell *cell,
 348                              const struct jailhouse_memory *mem)
 349 {
 350         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 351                               mem->size, PAGING_NON_COHERENT);
 352 }
 353
 354 void vcpu_vendor_cell_exit(struct cell *cell)
 355 {
 356         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 357                        PAGING_NON_COHERENT);
 358         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 359 }
 360
 361 int vcpu_init(struct per_cpu *cpu_data)
 362 {
 363         unsigned long efer;
 364         int err;
 365
 366         err = svm_check_features();
 367         if (err)
 368                 return err;
 369
 370         efer = read_msr(MSR_EFER);
 371         if (efer & EFER_SVME)
 372                 return trace_error(-EBUSY);
 373
 374         efer |= EFER_SVME;
 375         write_msr(MSR_EFER, efer);
 376
 377         cpu_data->svm_state = SVMON;
 378
 379         if (!vmcb_setup(cpu_data))
 380                 return trace_error(-EIO);
 381
 382         /*
 383          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 384          * set the values of reserved bits to the values found during the
 385          * previous CR0 read."
 386          * But we want to avoid surprises with new features unknown to us but
 387          * set by Linux. So check if any assumed revered bit was set and bail
 388          * out if so.
 389          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 390          */
 391         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 392                 return -EIO;
 393
 394         /* bring CR0 and CR4 into well-defined states */
 395         write_cr0(X86_CR0_HOST_STATE);
 396         write_cr4(X86_CR4_HOST_STATE);
 397
 398         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 399
 400         return 0;
 401 }
 402
 403 void vcpu_exit(struct per_cpu *cpu_data)
 404 {
 405         unsigned long efer;
 406
 407         if (cpu_data->svm_state == SVMOFF)
 408                 return;
 409
 410         cpu_data->svm_state = SVMOFF;
 411
 412         /* We are leaving - set the GIF */
 413         asm volatile ("stgi" : : : "memory");
 414
 415         efer = read_msr(MSR_EFER);
 416         efer &= ~EFER_SVME;
 417         write_msr(MSR_EFER, efer);
 418
 419         write_msr(MSR_VM_HSAVE_PA, 0);
 420 }
 421
 422 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 423 {
 424         unsigned long vmcb_pa, host_stack;
 425
 426         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 427         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 428
 429         /* We enter Linux at the point arch_entry would return to as well.
 430          * rax is cleared to signal success to the caller. */
 431         asm volatile(
 432                 "clgi\n\t"
 433                 "mov (%%rdi),%%r15\n\t"
 434                 "mov 0x8(%%rdi),%%r14\n\t"
 435                 "mov 0x10(%%rdi),%%r13\n\t"
 436                 "mov 0x18(%%rdi),%%r12\n\t"
 437                 "mov 0x20(%%rdi),%%rbx\n\t"
 438                 "mov 0x28(%%rdi),%%rbp\n\t"
 439                 "mov %0, %%rax\n\t"
 440                 "vmload %%rax\n\t"
 441                 "vmrun %%rax\n\t"
 442                 "vmsave %%rax\n\t"
 443                 /* Restore hypervisor stack */
 444                 "mov %2, %%rsp\n\t"
 445                 "jmp svm_vmexit"
 446                 : /* no output */
 447                 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
 448                 : "memory", "r15", "r14", "r13", "r12",
 449                   "rbx", "rbp", "rax", "cc");
 450         __builtin_unreachable();
 451 }
 452
 453 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
 454 {
 455         struct per_cpu *cpu_data = this_cpu_data();
 456         struct vmcb *vmcb = &cpu_data->vmcb;
 457         unsigned long *stack = (unsigned long *)vmcb->rsp;
 458         unsigned long linux_ip = vmcb->rip;
 459
 460         /*
 461          * Restore the MSRs.
 462          *
 463          * XXX: One could argue this is better to be done in
 464          * arch_cpu_restore(), however, it would require changes
 465          * to cpu_data to store STAR and friends.
 466          */
 467         write_msr(MSR_STAR, vmcb->star);
 468         write_msr(MSR_LSTAR, vmcb->lstar);
 469         write_msr(MSR_CSTAR, vmcb->cstar);
 470         write_msr(MSR_SFMASK, vmcb->sfmask);
 471         write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
 472
 473         cpu_data->linux_cr0 = vmcb->cr0;
 474         cpu_data->linux_cr3 = vmcb->cr3;
 475
 476         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 477         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 478         cpu_data->linux_idtr.base = vmcb->idtr.base;
 479         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 480
 481         cpu_data->linux_cs.selector = vmcb->cs.selector;
 482
 483         cpu_data->linux_tss.selector = vmcb->tr.selector;
 484
 485         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 486         cpu_data->linux_fs.base = vmcb->fs.base;
 487         cpu_data->linux_gs.base = vmcb->gs.base;
 488
 489         cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
 490         cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
 491         cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
 492
 493         cpu_data->linux_ds.selector = vmcb->ds.selector;
 494         cpu_data->linux_es.selector = vmcb->es.selector;
 495         cpu_data->linux_fs.selector = vmcb->fs.selector;
 496         cpu_data->linux_gs.selector = vmcb->gs.selector;
 497
 498         arch_cpu_restore(cpu_data, 0);
 499
 500         stack--;
 501         *stack = linux_ip;
 502
 503         asm volatile (
 504                 "mov %%rbx,%%rsp\n\t"
 505                 "pop %%r15\n\t"
 506                 "pop %%r14\n\t"
 507                 "pop %%r13\n\t"
 508                 "pop %%r12\n\t"
 509                 "pop %%r11\n\t"
 510                 "pop %%r10\n\t"
 511                 "pop %%r9\n\t"
 512                 "pop %%r8\n\t"
 513                 "pop %%rdi\n\t"
 514                 "pop %%rsi\n\t"
 515                 "pop %%rbp\n\t"
 516                 "add $8,%%rsp\n\t"
 517                 "pop %%rbx\n\t"
 518                 "pop %%rdx\n\t"
 519                 "pop %%rcx\n\t"
 520                 "mov %%rax,%%rsp\n\t"
 521                 "xor %%rax,%%rax\n\t"
 522                 "ret"
 523                 : : "a" (stack), "b" (&cpu_data->guest_regs));
 524         __builtin_unreachable();
 525 }
 526
 527 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 528 {
 529         static const struct svm_segment dataseg_reset_state = {
 530                 .selector = 0,
 531                 .base = 0,
 532                 .limit = 0xffff,
 533                 .access_rights = 0x0093,
 534         };
 535         static const struct svm_segment dtr_reset_state = {
 536                 .selector = 0,
 537                 .base = 0,
 538                 .limit = 0xffff,
 539                 .access_rights = 0,
 540         };
 541         struct vmcb *vmcb = &cpu_data->vmcb;
 542         unsigned long val;
 543         bool ok = true;
 544
 545         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 546         vmcb->cr3 = 0;
 547         vmcb->cr4 = 0;
 548
 549         vmcb->rflags = 0x02;
 550
 551         val = 0;
 552         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 553                 val = 0xfff0;
 554                 sipi_vector = 0xf0;
 555         }
 556         vmcb->rip = val;
 557         vmcb->rsp = 0;
 558
 559         vmcb->cs.selector = sipi_vector << 8;
 560         vmcb->cs.base = sipi_vector << 12;
 561         vmcb->cs.limit = 0xffff;
 562         vmcb->cs.access_rights = 0x009b;
 563
 564         vmcb->ds = dataseg_reset_state;
 565         vmcb->es = dataseg_reset_state;
 566         vmcb->fs = dataseg_reset_state;
 567         vmcb->gs = dataseg_reset_state;
 568         vmcb->ss = dataseg_reset_state;
 569
 570         vmcb->tr.selector = 0;
 571         vmcb->tr.base = 0;
 572         vmcb->tr.limit = 0xffff;
 573         vmcb->tr.access_rights = 0x008b;
 574
 575         vmcb->ldtr.selector = 0;
 576         vmcb->ldtr.base = 0;
 577         vmcb->ldtr.limit = 0xffff;
 578         vmcb->ldtr.access_rights = 0x0082;
 579
 580         vmcb->gdtr = dtr_reset_state;
 581         vmcb->idtr = dtr_reset_state;
 582
 583         vmcb->efer = EFER_SVME;
 584
 585         /* These MSRs are undefined on reset */
 586         vmcb->star = 0;
 587         vmcb->lstar = 0;
 588         vmcb->cstar = 0;
 589         vmcb->sfmask = 0;
 590         vmcb->sysenter_cs = 0;
 591         vmcb->sysenter_eip = 0;
 592         vmcb->sysenter_esp = 0;
 593         vmcb->kerngsbase = 0;
 594
 595         vmcb->dr7 = 0x00000400;
 596
 597         /* Almost all of the guest state changed */
 598         vmcb->clean_bits = 0;
 599
 600         ok &= svm_set_cell_config(cpu_data->cell, vmcb);
 601
 602         /* This is always false, but to be consistent with vmx.c... */
 603         if (!ok) {
 604                 panic_printk("FATAL: CPU reset failed\n");
 605                 panic_stop();
 606         }
 607 }
 608
 609 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 610 {
 611         this_cpu_data()->vmcb.rip += inst_len;
 612 }
 613
 614 static void update_efer(struct vmcb *vmcb)
 615 {
 616         unsigned long efer = vmcb->efer;
 617
 618         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 619                 return;
 620
 621         efer |= EFER_LMA;
 622
 623         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 624         if ((vmcb->efer ^ efer) & EFER_LMA)
 625                 vcpu_tlb_flush();
 626
 627         vmcb->efer = efer;
 628         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 629 }
 630
 631 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 632 {
 633         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 634
 635         if (vmcb->efer & EFER_LMA) {
 636                 pg_structs->root_paging = x86_64_paging;
 637                 pg_structs->root_table_gphys =
 638                         vmcb->cr3 & 0x000ffffffffff000UL;
 639         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 640                    !(vmcb->cr4 & X86_CR4_PAE)) {
 641                 pg_structs->root_paging = i386_paging;
 642                 pg_structs->root_table_gphys =
 643                         vmcb->cr3 & 0xfffff000UL;
 644         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 645                 /*
 646                  * Can be in non-paged protected mode as well, but
 647                  * the translation mechanism will stay the same ayway.
 648                  */
 649                 pg_structs->root_paging = realmode_paging;
 650                 /*
 651                  * This will make paging_get_guest_pages map the page
 652                  * that also contains the bootstrap code and, thus, is
 653                  * always present in a cell.
 654                  */
 655                 pg_structs->root_table_gphys = 0xff000;
 656         } else {
 657                 printk("FATAL: Unsupported paging mode\n");
 658                 return false;
 659         }
 660         return true;
 661 }
 662
 663 void vcpu_vendor_set_guest_pat(unsigned long val)
 664 {
 665         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 666
 667         vmcb->g_pat = val;
 668         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 669 }
 670
 671 struct parse_context {
 672         unsigned int remaining;
 673         unsigned int size;
 674         unsigned long cs_base;
 675         const u8 *inst;
 676 };
 677
 678 static bool ctx_advance(struct parse_context *ctx,
 679                         unsigned long *pc,
 680                         struct guest_paging_structures *pg_structs)
 681 {
 682         if (!ctx->size) {
 683                 ctx->size = ctx->remaining;
 684                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 685                                           &ctx->size);
 686                 if (!ctx->inst)
 687                         return false;
 688                 ctx->remaining -= ctx->size;
 689                 *pc += ctx->size;
 690         }
 691         return true;
 692 }
 693
 694 static bool svm_parse_mov_to_cr(struct vmcb *vmcb, unsigned long pc,
 695                                 unsigned char reg, unsigned long *gpr)
 696 {
 697         struct guest_paging_structures pg_structs;
 698         struct parse_context ctx = {};
 699         /* No prefixes are supported yet */
 700         u8 opcodes[] = {0x0f, 0x22}, modrm;
 701         bool ok = false;
 702         int n;
 703
 704         ctx.remaining = ARRAY_SIZE(opcodes);
 705         if (!vcpu_get_guest_paging_structs(&pg_structs))
 706                 goto out;
 707         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 708
 709         if (!ctx_advance(&ctx, &pc, &pg_structs))
 710                 goto out;
 711
 712         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
 713                 if (*(ctx.inst) != opcodes[n])
 714                         goto out;
 715                 if (!ctx_advance(&ctx, &pc, &pg_structs))
 716                         goto out;
 717         }
 718
 719         if (!ctx_advance(&ctx, &pc, &pg_structs))
 720                 goto out;
 721
 722         modrm = *(ctx.inst);
 723
 724         if (((modrm & 0x38) >> 3) != reg)
 725                 goto out;
 726
 727         if (gpr)
 728                 *gpr = (modrm & 0x7);
 729
 730         ok = true;
 731 out:
 732         return ok;
 733 }
 734
 735 /*
 736  * XXX: The only visible reason to have this function (vmx.c consistency
 737  * aside) is to prevent cells from setting invalid CD+NW combinations that
 738  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 739  * altogether?
 740  */
 741 static bool svm_handle_cr(struct per_cpu *cpu_data)
 742 {
 743         struct vmcb *vmcb = &cpu_data->vmcb;
 744         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 745         unsigned long reg = -1, val, bits;
 746         bool ok = true;
 747
 748         if (has_assists) {
 749                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 750                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 751                         ok = false;
 752                         goto out;
 753                 }
 754                 reg = vmcb->exitinfo1 & 0x07;
 755         } else {
 756                 if (!svm_parse_mov_to_cr(vmcb, vmcb->rip, 0, &reg)) {
 757                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 758                         ok = false;
 759                         goto out;
 760                 }
 761         };
 762
 763         if (reg == 4)
 764                 val = vmcb->rsp;
 765         else
 766                 val = cpu_data->guest_regs.by_index[15 - reg];
 767
 768         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 769         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 770         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 771         if ((val ^ vmcb->cr0) & bits)
 772                 vcpu_tlb_flush();
 773         /* TODO: better check for #GP reasons */
 774         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 775         if (val & X86_CR0_PG)
 776                 update_efer(vmcb);
 777         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 778
 779 out:
 780         return ok;
 781 }
 782
 783 static bool svm_handle_msr_write(struct per_cpu *cpu_data)
 784 {
 785         struct vmcb *vmcb = &cpu_data->vmcb;
 786         unsigned long efer;
 787
 788         if (cpu_data->guest_regs.rcx == MSR_EFER) {
 789                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 790                 efer = get_wrmsr_value(&cpu_data->guest_regs) | EFER_SVME;
 791                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 792                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 793                         vcpu_tlb_flush();
 794                 vmcb->efer = efer;
 795                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 796                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 797                 return true;
 798         }
 799
 800         return vcpu_handle_msr_write();
 801 }
 802
 803 /*
 804  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 805  * be treated separately in svm_handle_avic_access().
 806  */
 807 static bool svm_handle_apic_access(struct vmcb *vmcb)
 808 {
 809         struct guest_paging_structures pg_structs;
 810         unsigned int inst_len, offset;
 811         bool is_write;
 812
 813         /* The caller is responsible for sanity checks */
 814         is_write = !!(vmcb->exitinfo1 & 0x2);
 815         offset = vmcb->exitinfo2 - XAPIC_BASE;
 816
 817         if (offset & 0x00f)
 818                 goto out_err;
 819
 820         if (!vcpu_get_guest_paging_structs(&pg_structs))
 821                 goto out_err;
 822
 823         inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
 824                                     is_write);
 825         if (!inst_len)
 826                 goto out_err;
 827
 828         vcpu_skip_emulated_instruction(inst_len);
 829         return true;
 830
 831 out_err:
 832         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 833                      offset, is_write);
 834         return false;
 835 }
 836
 837 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
 838 {
 839         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 840                      vmcb->rsp, vmcb->rflags);
 841         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 842                      guest_regs->rbx, guest_regs->rcx);
 843         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 844                      guest_regs->rsi, guest_regs->rdi);
 845         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 846                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 847                      !!(vmcb->efer & EFER_LMA));
 848         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 849                      vmcb->cr3, vmcb->cr4);
 850         panic_printk("EFER: %p\n", vmcb->efer);
 851 }
 852
 853 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
 854 {
 855         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 856         u64 exitinfo = vmcb->exitinfo1;
 857
 858         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 859         io->port = (exitinfo >> 16) & 0xFFFF;
 860         io->size = (exitinfo >> 4) & 0x7;
 861         io->in = !!(exitinfo & 0x1);
 862         io->inst_len = vmcb->exitinfo2 - vmcb->rip;
 863         io->rep_or_str = !!(exitinfo & 0x0c);
 864 }
 865
 866 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
 867 {
 868         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 869
 870         mmio->phys_addr = vmcb->exitinfo2;
 871         mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
 872 }
 873
 874 void vcpu_handle_exit(struct per_cpu *cpu_data)
 875 {
 876         struct vmcb *vmcb = &cpu_data->vmcb;
 877         bool res = false;
 878         int sipi_vector;
 879
 880         /* Restore GS value expected by per_cpu data accessors */
 881         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 882
 883         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 884         /*
 885          * All guest state is marked unmodified; individual handlers must clear
 886          * the bits as needed.
 887          */
 888         vmcb->clean_bits = 0xffffffff;
 889
 890         switch (vmcb->exitcode) {
 891         case VMEXIT_INVALID:
 892                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 893                              vmcb->exitcode);
 894                 break;
 895         case VMEXIT_NMI:
 896                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 897                 /* Temporarily enable GIF to consume pending NMI */
 898                 asm volatile("stgi; clgi" : : : "memory");
 899                 sipi_vector = x86_handle_events(cpu_data);
 900                 if (sipi_vector >= 0) {
 901                         printk("CPU %d received SIPI, vector %x\n",
 902                                cpu_data->cpu_id, sipi_vector);
 903                         svm_vcpu_reset(cpu_data, sipi_vector);
 904                         vcpu_reset();
 905                 }
 906                 iommu_check_pending_faults(cpu_data);
 907                 return;
 908         case VMEXIT_VMMCALL:
 909                 vcpu_handle_hypercall();
 910                 return;
 911         case VMEXIT_CR0_SEL_WRITE:
 912                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 913                 if (svm_handle_cr(cpu_data))
 914                         return;
 915                 break;
 916         case VMEXIT_MSR:
 917                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 918                 if (!vmcb->exitinfo1)
 919                         res = vcpu_handle_msr_read();
 920                 else
 921                         res = svm_handle_msr_write(cpu_data);
 922                 if (res)
 923                         return;
 924                 break;
 925         case VMEXIT_NPF:
 926                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
 927                      vmcb->exitinfo2 >= XAPIC_BASE &&
 928                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
 929                         /* APIC access in non-AVIC mode */
 930                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
 931                         if (svm_handle_apic_access(vmcb))
 932                                 return;
 933                 } else {
 934                         /* General MMIO (IOAPIC, PCI etc) */
 935                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
 936                         if (vcpu_handle_mmio_access())
 937                                 return;
 938                 }
 939
 940                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
 941                              "error code is %x\n", vmcb->exitinfo2,
 942                              vmcb->exitinfo1 & 0xf);
 943                 break;
 944         case VMEXIT_XSETBV:
 945                 if (vcpu_handle_xsetbv())
 946                         return;
 947                 break;
 948         case VMEXIT_IOIO:
 949                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
 950                 if (vcpu_handle_io_access())
 951                         return;
 952                 break;
 953         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
 954         default:
 955                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
 956                              "exitinfo1 %p exitinfo2 %p\n",
 957                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
 958         }
 959         dump_guest_regs(&cpu_data->guest_regs, vmcb);
 960         panic_park();
 961 }
 962
 963 void vcpu_park(void)
 964 {
 965         svm_vcpu_reset(this_cpu_data(), APIC_BSP_PSEUDO_SIPI);
 966         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
 967         this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
 968
 969         vcpu_tlb_flush();
 970 }
 971
 972 void vcpu_nmi_handler(void)
 973 {
 974 }
 975
 976 void vcpu_tlb_flush(void)
 977 {
 978         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 979
 980         if (has_flush_by_asid)
 981                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
 982         else
 983                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
 984 }
 985
 986 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
 987                               unsigned long pc, unsigned int *size)
 988 {
 989         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 990         unsigned long start;
 991
 992         if (has_assists) {
 993                 if (!*size)
 994                         return NULL;
 995                 start = vmcb->rip - pc;
 996                 if (start < vmcb->bytes_fetched) {
 997                         *size = vmcb->bytes_fetched - start;
 998                         return &vmcb->guest_bytes[start];
 999                 } else {
1000                         return NULL;
1001                 }
1002         } else {
1003                 return vcpu_map_inst(pg_structs, pc, size);
1004         }
1005 }
1006
1007 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1008                                     struct vcpu_io_bitmap *iobm)
1009 {
1010         iobm->data = cell->svm.iopm;
1011         iobm->size = sizeof(cell->svm.iopm);
1012 }
1013
1014 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1015 {
1016         struct vmcb *vmcb = &this_cpu_data()->vmcb;
1017
1018         x_state->efer = vmcb->efer;
1019         x_state->rflags = vmcb->rflags;
1020         x_state->cs = vmcb->cs.selector;
1021         x_state->rip = vmcb->rip;
1022 }
1023
1024 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1025 void enable_irq(void)
1026 {
1027         asm volatile("stgi; sti" : : : "memory");
1028 }
1029
1030 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1031 void disable_irq(void)
1032 {
1033         asm volatile("cli; clgi" : : : "memory");
1034 }