hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 #define MTRR_DEFTYPE            0x2ff
  43
  44 static bool has_avic, has_assists, has_flush_by_asid;
  45
  46 static const struct segment invalid_seg;
  47
  48 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  49
  50 /* bit cleared: direct access allowed */
  51 // TODO: convert to whitelist
  52 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  53         [ SVM_MSRPM_0000 ] = {
  54                 [      0/4 ...  0x017/4 ] = 0,
  55                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  56                 [  0x01c/4 ...  0x273/4 ] = 0,
  57                 [  0x274/4 ...  0x277/4 ] = 0xc0, /* 0x277 (rw) */
  58                 [  0x278/4 ...  0x2fb/4 ] = 0,
  59                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  60                 [  0x300/4 ...  0x7ff/4 ] = 0,
  61                 /* x2APIC MSRs - emulated if not present */
  62                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  63                 [  0x804/4 ...  0x807/4 ] = 0,
  64                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  65                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  66                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  67                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  68                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  69                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  70                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  71                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  72                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  73                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  74                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  75                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  76                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  77                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  78                 [  0x840/4 ... 0x1fff/4 ] = 0,
  79         },
  80         [ SVM_MSRPM_C000 ] = {
  81                 [      0/4 ...  0x07f/4 ] = 0,
  82                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  83                 [  0x084/4 ... 0x1fff/4 ] = 0
  84         },
  85         [ SVM_MSRPM_C001 ] = {
  86                 [      0/4 ... 0x1fff/4 ] = 0,
  87         },
  88         [ SVM_MSRPM_RESV ] = {
  89                 [      0/4 ... 0x1fff/4 ] = 0,
  90         }
  91 };
  92
  93 /* This page is mapped so the code begins at 0x000ffff0 */
  94 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  95         [0xff0] = 0xfa, /* 1: cli */
  96         [0xff1] = 0xf4, /*    hlt */
  97         [0xff2] = 0xeb,
  98         [0xff3] = 0xfc  /*    jmp 1b */
  99 };
 100
 101 static void *parked_mode_npt;
 102
 103 static void *avic_page;
 104
 105 static int svm_check_features(void)
 106 {
 107         /* SVM is available */
 108         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 109                 return trace_error(-ENODEV);
 110
 111         /* Nested paging */
 112         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 113                 return trace_error(-EIO);
 114
 115         /* Decode assists */
 116         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 117                 has_assists = true;
 118
 119         /* AVIC support */
 120         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 121                 has_avic = true;
 122
 123         /* TLB Flush by ASID support */
 124         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 125                 has_flush_by_asid = true;
 126
 127         return 0;
 128 }
 129
 130 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 131                                      const struct desc_table_reg *dtr)
 132 {
 133         struct svm_segment tmp = { 0 };
 134
 135         if (dtr) {
 136                 tmp.base = dtr->base;
 137                 tmp.limit = dtr->limit & 0xffff;
 138         }
 139
 140         *svm_segment = tmp;
 141 }
 142
 143 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
 144 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 145                                          const struct segment *segment)
 146 {
 147         u32 ar;
 148
 149         svm_segment->selector = segment->selector;
 150
 151         if (segment->access_rights == 0x10000) {
 152                 svm_segment->access_rights = 0;
 153         } else {
 154                 ar = segment->access_rights;
 155                 svm_segment->access_rights =
 156                         ((ar & 0xf000) >> 4) | (ar & 0x00ff);
 157         }
 158
 159         svm_segment->limit = segment->limit;
 160         svm_segment->base = segment->base;
 161 }
 162
 163 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 164 {
 165         /* No real need for this function; used for consistency with vmx.c */
 166         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 167         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 168
 169         return true;
 170 }
 171
 172 static int vmcb_setup(struct per_cpu *cpu_data)
 173 {
 174         struct vmcb *vmcb = &cpu_data->vmcb;
 175
 176         memset(vmcb, 0, sizeof(struct vmcb));
 177
 178         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 179         vmcb->cr3 = cpu_data->linux_cr3;
 180         vmcb->cr4 = cpu_data->linux_cr4;
 181
 182         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 183         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 184         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 185         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 186         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 187         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 188         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 189
 190         set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
 191         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 192         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 193
 194         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 195
 196         vmcb->rflags = 0x02;
 197         /* Indicate success to the caller of arch_entry */
 198         vmcb->rax = 0;
 199         vmcb->rsp = cpu_data->linux_sp +
 200                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 201         vmcb->rip = cpu_data->linux_ip;
 202
 203         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 204         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 205         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 206         vmcb->star = read_msr(MSR_STAR);
 207         vmcb->lstar = read_msr(MSR_LSTAR);
 208         vmcb->cstar = read_msr(MSR_CSTAR);
 209         vmcb->sfmask = read_msr(MSR_SFMASK);
 210         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 211
 212         vmcb->dr6 = 0x00000ff0;
 213         vmcb->dr7 = 0x00000400;
 214
 215         /* Make the hypervisor visible */
 216         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 217
 218         vmcb->g_pat = cpu_data->pat;
 219
 220         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 221         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 222         /* TODO: Do we need this for SVM ? */
 223         /* vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID; */
 224         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 225         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 226         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 227
 228         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 229         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 230
 231         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 232
 233         vmcb->np_enable = 1;
 234         /* No more than one guest owns the CPU */
 235         vmcb->guest_asid = 1;
 236
 237         /* TODO: Setup AVIC */
 238
 239         /* Explicitly mark all of the state as new */
 240         vmcb->clean_bits = 0;
 241
 242         return svm_set_cell_config(cpu_data->cell, vmcb);
 243 }
 244
 245 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 246                                      unsigned long gphys,
 247                                      unsigned long flags)
 248 {
 249         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 250                         gphys, flags);
 251 }
 252
 253 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 254 {
 255         /* See APMv2, Section 15.25.5 */
 256         *pte = (next_pt & 0x000ffffffffff000UL) |
 257                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 258 }
 259
 260 int vcpu_vendor_init(void)
 261 {
 262         struct paging_structures parking_pt;
 263         unsigned long vm_cr;
 264         int err, n;
 265
 266         err = svm_check_features();
 267         if (err)
 268                 return err;
 269
 270         vm_cr = read_msr(MSR_VM_CR);
 271         if (vm_cr & VM_CR_SVMDIS)
 272                 /* SVM disabled in BIOS */
 273                 return trace_error(-EPERM);
 274
 275         /* Nested paging is the same as the native one */
 276         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 277         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 278                 npt_paging[n].set_next_pt = npt_set_next_pt;
 279
 280         /* Map guest parking code (shared between cells and CPUs) */
 281         parking_pt.root_paging = npt_paging;
 282         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 283         if (!parked_mode_npt)
 284                 return -ENOMEM;
 285         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 286                             PAGE_SIZE, 0x000ff000,
 287                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 288                             PAGING_NON_COHERENT);
 289         if (err)
 290                 return err;
 291
 292         /* This is always false for AMD now (except in nested SVM);
 293            see Sect. 16.3.1 in APMv2 */
 294         if (using_x2apic) {
 295                 /* allow direct x2APIC access except for ICR writes */
 296                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 297                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 298                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 299         } else {
 300                 if (has_avic) {
 301                         avic_page = page_alloc(&remap_pool, 1);
 302                         if (!avic_page)
 303                                 return trace_error(-ENOMEM);
 304                 }
 305         }
 306
 307         return vcpu_cell_init(&root_cell);
 308 }
 309
 310 int vcpu_vendor_cell_init(struct cell *cell)
 311 {
 312         u64 flags;
 313         int err;
 314
 315         /* allocate iopm (two 4-K pages + 3 bits) */
 316         cell->svm.iopm = page_alloc(&mem_pool, 3);
 317         if (!cell->svm.iopm)
 318                 return -ENOMEM;
 319
 320         /* build root NPT of cell */
 321         cell->svm.npt_structs.root_paging = npt_paging;
 322         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 323         if (!cell->svm.npt_structs.root_table)
 324                 return -ENOMEM;
 325
 326         if (!has_avic) {
 327                 /*
 328                  * Map xAPIC as is; reads are passed, writes are trapped.
 329                  */
 330                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 331                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 332                                     PAGE_SIZE, XAPIC_BASE,
 333                                     flags,
 334                                     PAGING_NON_COHERENT);
 335         } else {
 336                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 337                 err = paging_create(&cell->svm.npt_structs,
 338                                     paging_hvirt2phys(avic_page),
 339                                     PAGE_SIZE, XAPIC_BASE,
 340                                     flags,
 341                                     PAGING_NON_COHERENT);
 342         }
 343
 344         return err;
 345 }
 346
 347 int vcpu_map_memory_region(struct cell *cell,
 348                            const struct jailhouse_memory *mem)
 349 {
 350         u64 phys_start = mem->phys_start;
 351         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 352
 353         if (mem->flags & JAILHOUSE_MEM_READ)
 354                 flags |= PAGE_FLAG_PRESENT;
 355         if (mem->flags & JAILHOUSE_MEM_WRITE)
 356                 flags |= PAGE_FLAG_RW;
 357         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 358                 flags |= PAGE_FLAG_NOEXECUTE;
 359         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 360                 phys_start = paging_hvirt2phys(&cell->comm_page);
 361
 362         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 363                              mem->virt_start, flags, PAGING_NON_COHERENT);
 364 }
 365
 366 int vcpu_unmap_memory_region(struct cell *cell,
 367                              const struct jailhouse_memory *mem)
 368 {
 369         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 370                               mem->size, PAGING_NON_COHERENT);
 371 }
 372
 373 void vcpu_vendor_cell_exit(struct cell *cell)
 374 {
 375         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 376                        PAGING_NON_COHERENT);
 377         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 378 }
 379
 380 int vcpu_init(struct per_cpu *cpu_data)
 381 {
 382         unsigned long efer;
 383         int err;
 384
 385         err = svm_check_features();
 386         if (err)
 387                 return err;
 388
 389         efer = read_msr(MSR_EFER);
 390         if (efer & EFER_SVME)
 391                 return trace_error(-EBUSY);
 392
 393         efer |= EFER_SVME;
 394         write_msr(MSR_EFER, efer);
 395
 396         cpu_data->svm_state = SVMON;
 397
 398         if (!vmcb_setup(cpu_data))
 399                 return trace_error(-EIO);
 400
 401         /*
 402          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 403          * set the values of reserved bits to the values found during the
 404          * previous CR0 read."
 405          * But we want to avoid surprises with new features unknown to us but
 406          * set by Linux. So check if any assumed revered bit was set and bail
 407          * out if so.
 408          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 409          */
 410         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 411                 return -EIO;
 412
 413         /* bring CR0 and CR4 into well-defined states */
 414         write_cr0(X86_CR0_HOST_STATE);
 415         write_cr4(X86_CR4_HOST_STATE);
 416
 417         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 418
 419         return 0;
 420 }
 421
 422 void vcpu_exit(struct per_cpu *cpu_data)
 423 {
 424         unsigned long efer;
 425
 426         if (cpu_data->svm_state == SVMOFF)
 427                 return;
 428
 429         cpu_data->svm_state = SVMOFF;
 430
 431         /* We are leaving - set the GIF */
 432         asm volatile ("stgi" : : : "memory");
 433
 434         efer = read_msr(MSR_EFER);
 435         efer &= ~EFER_SVME;
 436         write_msr(MSR_EFER, efer);
 437
 438         write_msr(MSR_VM_HSAVE_PA, 0);
 439 }
 440
 441 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 442 {
 443         unsigned long vmcb_pa, host_stack;
 444
 445         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 446         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 447
 448         /* We enter Linux at the point arch_entry would return to as well.
 449          * rax is cleared to signal success to the caller. */
 450         asm volatile(
 451                 "clgi\n\t"
 452                 "mov (%%rdi),%%r15\n\t"
 453                 "mov 0x8(%%rdi),%%r14\n\t"
 454                 "mov 0x10(%%rdi),%%r13\n\t"
 455                 "mov 0x18(%%rdi),%%r12\n\t"
 456                 "mov 0x20(%%rdi),%%rbx\n\t"
 457                 "mov 0x28(%%rdi),%%rbp\n\t"
 458                 "mov %0, %%rax\n\t"
 459                 "vmload %%rax\n\t"
 460                 "vmrun %%rax\n\t"
 461                 "vmsave %%rax\n\t"
 462                 /* Restore hypervisor stack */
 463                 "mov %2, %%rsp\n\t"
 464                 "jmp svm_vmexit"
 465                 : /* no output */
 466                 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
 467                 : "memory", "r15", "r14", "r13", "r12",
 468                   "rbx", "rbp", "rax", "cc");
 469         __builtin_unreachable();
 470 }
 471
 472 void __attribute__((noreturn))
 473 vcpu_deactivate_vmm(struct registers *guest_regs)
 474 {
 475         struct per_cpu *cpu_data = this_cpu_data();
 476         struct vmcb *vmcb = &cpu_data->vmcb;
 477         unsigned long *stack = (unsigned long *)vmcb->rsp;
 478         unsigned long linux_ip = vmcb->rip;
 479
 480         /*
 481          * Restore the MSRs.
 482          *
 483          * XXX: One could argue this is better to be done in
 484          * arch_cpu_restore(), however, it would require changes
 485          * to cpu_data to store STAR and friends.
 486          */
 487         write_msr(MSR_STAR, vmcb->star);
 488         write_msr(MSR_LSTAR, vmcb->lstar);
 489         write_msr(MSR_CSTAR, vmcb->cstar);
 490         write_msr(MSR_SFMASK, vmcb->sfmask);
 491         write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
 492
 493         cpu_data->linux_cr0 = vmcb->cr0;
 494         cpu_data->linux_cr3 = vmcb->cr3;
 495
 496         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 497         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 498         cpu_data->linux_idtr.base = vmcb->idtr.base;
 499         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 500
 501         cpu_data->linux_cs.selector = vmcb->cs.selector;
 502
 503         cpu_data->linux_tss.selector = vmcb->tr.selector;
 504
 505         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 506         cpu_data->linux_fs.base = vmcb->fs.base;
 507         cpu_data->linux_gs.base = vmcb->gs.base;
 508
 509         cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
 510         cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
 511         cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
 512
 513         cpu_data->linux_ds.selector = vmcb->ds.selector;
 514         cpu_data->linux_es.selector = vmcb->es.selector;
 515         cpu_data->linux_fs.selector = vmcb->fs.selector;
 516         cpu_data->linux_gs.selector = vmcb->gs.selector;
 517
 518         arch_cpu_restore(cpu_data, 0);
 519
 520         stack--;
 521         *stack = linux_ip;
 522
 523         asm volatile (
 524                 "mov %%rbx,%%rsp\n\t"
 525                 "pop %%r15\n\t"
 526                 "pop %%r14\n\t"
 527                 "pop %%r13\n\t"
 528                 "pop %%r12\n\t"
 529                 "pop %%r11\n\t"
 530                 "pop %%r10\n\t"
 531                 "pop %%r9\n\t"
 532                 "pop %%r8\n\t"
 533                 "pop %%rdi\n\t"
 534                 "pop %%rsi\n\t"
 535                 "pop %%rbp\n\t"
 536                 "add $8,%%rsp\n\t"
 537                 "pop %%rbx\n\t"
 538                 "pop %%rdx\n\t"
 539                 "pop %%rcx\n\t"
 540                 "mov %%rax,%%rsp\n\t"
 541                 "xor %%rax,%%rax\n\t"
 542                 "ret"
 543                 : : "a" (stack), "b" (guest_regs));
 544         __builtin_unreachable();
 545 }
 546
 547 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 548 {
 549         struct vmcb *vmcb = &cpu_data->vmcb;
 550         unsigned long val;
 551         bool ok = true;
 552
 553         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 554         vmcb->cr3 = 0;
 555         vmcb->cr4 = 0;
 556
 557         vmcb->rflags = 0x02;
 558
 559         val = 0;
 560         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 561                 val = 0xfff0;
 562                 sipi_vector = 0xf0;
 563         }
 564         vmcb->rip = val;
 565         vmcb->rsp = 0;
 566
 567         vmcb->cs.selector = sipi_vector << 8;
 568         vmcb->cs.base = sipi_vector << 12;
 569         vmcb->cs.limit = 0xffff;
 570         vmcb->cs.access_rights = 0x009b;
 571
 572         vmcb->ds.selector = 0;
 573         vmcb->ds.base = 0;
 574         vmcb->ds.limit = 0xffff;
 575         vmcb->ds.access_rights = 0x0093;
 576
 577         vmcb->es.selector = 0;
 578         vmcb->es.base = 0;
 579         vmcb->es.limit = 0xffff;
 580         vmcb->es.access_rights = 0x0093;
 581
 582         vmcb->fs.selector = 0;
 583         vmcb->fs.base = 0;
 584         vmcb->fs.limit = 0xffff;
 585         vmcb->fs.access_rights = 0x0093;
 586
 587         vmcb->gs.selector = 0;
 588         vmcb->gs.base = 0;
 589         vmcb->gs.limit = 0xffff;
 590         vmcb->gs.access_rights = 0x0093;
 591
 592         vmcb->ss.selector = 0;
 593         vmcb->ss.base = 0;
 594         vmcb->ss.limit = 0xffff;
 595         vmcb->ss.access_rights = 0x0093;
 596
 597         vmcb->tr.selector = 0;
 598         vmcb->tr.base = 0;
 599         vmcb->tr.limit = 0xffff;
 600         vmcb->tr.access_rights = 0x008b;
 601
 602         vmcb->ldtr.selector = 0;
 603         vmcb->ldtr.base = 0;
 604         vmcb->ldtr.limit = 0xffff;
 605         vmcb->ldtr.access_rights = 0x0082;
 606
 607         vmcb->gdtr.selector = 0;
 608         vmcb->gdtr.base = 0;
 609         vmcb->gdtr.limit = 0xffff;
 610         vmcb->gdtr.access_rights = 0;
 611
 612         vmcb->idtr.selector = 0;
 613         vmcb->idtr.base = 0;
 614         vmcb->idtr.limit = 0xffff;
 615         vmcb->idtr.access_rights = 0;
 616
 617         vmcb->efer = EFER_SVME;
 618
 619         /* These MSRs are undefined on reset */
 620         vmcb->star = 0;
 621         vmcb->lstar = 0;
 622         vmcb->cstar = 0;
 623         vmcb->sfmask = 0;
 624         vmcb->sysenter_cs = 0;
 625         vmcb->sysenter_eip = 0;
 626         vmcb->sysenter_esp = 0;
 627         vmcb->kerngsbase = 0;
 628
 629         vmcb->dr7 = 0x00000400;
 630
 631         /* Almost all of the guest state changed */
 632         vmcb->clean_bits = 0;
 633
 634         ok &= svm_set_cell_config(cpu_data->cell, vmcb);
 635
 636         /* This is always false, but to be consistent with vmx.c... */
 637         if (!ok) {
 638                 panic_printk("FATAL: CPU reset failed\n");
 639                 panic_stop();
 640         }
 641 }
 642
 643 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 644 {
 645         struct per_cpu *cpu_data = this_cpu_data();
 646         struct vmcb *vmcb = &cpu_data->vmcb;
 647         vmcb->rip += inst_len;
 648 }
 649
 650 static void update_efer(struct per_cpu *cpu_data)
 651 {
 652         struct vmcb *vmcb = &cpu_data->vmcb;
 653         unsigned long efer = vmcb->efer;
 654
 655         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 656                 return;
 657
 658         efer |= EFER_LMA;
 659
 660         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 661         if ((vmcb->efer ^ efer) & EFER_LMA)
 662                 vcpu_tlb_flush();
 663
 664         vmcb->efer = efer;
 665         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 666 }
 667
 668 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 669 {
 670         struct per_cpu *cpu_data = this_cpu_data();
 671         struct vmcb *vmcb = &cpu_data->vmcb;
 672
 673         if (vmcb->efer & EFER_LMA) {
 674                 pg_structs->root_paging = x86_64_paging;
 675                 pg_structs->root_table_gphys =
 676                         vmcb->cr3 & 0x000ffffffffff000UL;
 677         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 678                    !(vmcb->cr4 & X86_CR4_PAE)) {
 679                 pg_structs->root_paging = i386_paging;
 680                 pg_structs->root_table_gphys =
 681                         vmcb->cr3 & 0xfffff000UL;
 682         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 683                 /*
 684                  * Can be in non-paged protected mode as well, but
 685                  * the translation mechanism will stay the same ayway.
 686                  */
 687                 pg_structs->root_paging = realmode_paging;
 688                 /*
 689                  * This will make paging_get_guest_pages map the page
 690                  * that also contains the bootstrap code and, thus, is
 691                  * always present in a cell.
 692                  */
 693                 pg_structs->root_table_gphys = 0xff000;
 694         } else {
 695                 printk("FATAL: Unsupported paging mode\n");
 696                 return false;
 697         }
 698         return true;
 699 }
 700
 701 void vcpu_vendor_set_guest_pat(unsigned long val)
 702 {
 703         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 704
 705         vmcb->g_pat = val;
 706         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 707 }
 708
 709 struct parse_context {
 710         unsigned int remaining;
 711         unsigned int size;
 712         unsigned long cs_base;
 713         const u8 *inst;
 714 };
 715
 716 static bool ctx_advance(struct parse_context *ctx,
 717                         unsigned long *pc,
 718                         struct guest_paging_structures *pg_structs)
 719 {
 720         if (!ctx->size) {
 721                 ctx->size = ctx->remaining;
 722                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 723                                           &ctx->size);
 724                 if (!ctx->inst)
 725                         return false;
 726                 ctx->remaining -= ctx->size;
 727                 *pc += ctx->size;
 728         }
 729         return true;
 730 }
 731
 732 static bool x86_parse_mov_to_cr(struct per_cpu *cpu_data,
 733                                 unsigned long pc,
 734                                 unsigned char reg,
 735                                 unsigned long *gpr)
 736 {
 737         struct guest_paging_structures pg_structs;
 738         struct vmcb *vmcb = &cpu_data->vmcb;
 739         struct parse_context ctx = {};
 740         /* No prefixes are supported yet */
 741         u8 opcodes[] = {0x0f, 0x22}, modrm;
 742         bool ok = false;
 743         int n;
 744
 745         ctx.remaining = ARRAY_SIZE(opcodes);
 746         if (!vcpu_get_guest_paging_structs(&pg_structs))
 747                 goto out;
 748         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 749
 750         if (!ctx_advance(&ctx, &pc, &pg_structs))
 751                 goto out;
 752
 753         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
 754                 if (*(ctx.inst) != opcodes[n])
 755                         goto out;
 756                 if (!ctx_advance(&ctx, &pc, &pg_structs))
 757                         goto out;
 758         }
 759
 760         if (!ctx_advance(&ctx, &pc, &pg_structs))
 761                 goto out;
 762
 763         modrm = *(ctx.inst);
 764
 765         if (((modrm & 0x38) >> 3) != reg)
 766                 goto out;
 767
 768         if (gpr)
 769                 *gpr = (modrm & 0x7);
 770
 771         ok = true;
 772 out:
 773         return ok;
 774 }
 775
 776 /*
 777  * XXX: The only visible reason to have this function (vmx.c consistency
 778  * aside) is to prevent cells from setting invalid CD+NW combinations that
 779  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 780  * altogether?
 781  */
 782 static bool svm_handle_cr(struct registers *guest_regs,
 783                           struct per_cpu *cpu_data)
 784 {
 785         struct vmcb *vmcb = &cpu_data->vmcb;
 786         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 787         unsigned long reg = -1, val, bits;
 788         bool ok = true;
 789
 790         if (has_assists) {
 791                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 792                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 793                         ok = false;
 794                         goto out;
 795                 }
 796                 reg = vmcb->exitinfo1 & 0x07;
 797         } else {
 798                 if (!x86_parse_mov_to_cr(cpu_data, vmcb->rip, 0, &reg)) {
 799                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 800                         ok = false;
 801                         goto out;
 802                 }
 803         };
 804
 805         if (reg == 4)
 806                 val = vmcb->rsp;
 807         else
 808                 val = ((unsigned long *)guest_regs)[15 - reg];
 809
 810         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 811         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 812         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 813         if ((val ^ vmcb->cr0) & bits)
 814                 vcpu_tlb_flush();
 815         /* TODO: better check for #GP reasons */
 816         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 817         if (val & X86_CR0_PG)
 818                 update_efer(cpu_data);
 819         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 820
 821 out:
 822         return ok;
 823 }
 824
 825 static bool svm_handle_msr_write(struct registers *guest_regs,
 826                 struct per_cpu *cpu_data)
 827 {
 828         struct vmcb *vmcb = &cpu_data->vmcb;
 829         unsigned long efer, val;
 830
 831         switch (guest_regs->rcx) {
 832         case MSR_EFER:
 833                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 834                 efer = get_wrmsr_value(guest_regs) | EFER_SVME;
 835                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 836                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 837                         vcpu_tlb_flush();
 838                 vmcb->efer = efer;
 839                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 840                 break;
 841         case MTRR_DEFTYPE:
 842                 val = get_wrmsr_value(guest_regs);
 843                 /*
 844                  * Quick (and very incomplete) guest MTRRs emulation.
 845                  *
 846                  * For Linux, emulating MTRR Enable bit seems to be enough.
 847                  * If it is cleared, we set hPAT to all zeroes, effectively
 848                  * making all NPT-mapped memory UC (see APMv2, Sect. 15.25.8).
 849                  *
 850                  * Otherwise, default PAT value is restored. This can also
 851                  * make NPT-mapped memory's type different from what Linux
 852                  * expects, however.
 853                  */
 854                 if (val & 0x800)
 855                         write_msr(MSR_IA32_PAT, PAT_RESET_VALUE);
 856                 else
 857                         write_msr(MSR_IA32_PAT, 0);
 858                 break;
 859         default:
 860                 return vcpu_handle_msr_write(guest_regs);
 861         }
 862
 863         vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 864         return true;
 865 }
 866
 867 /*
 868  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 869  * be treated separately in svm_handle_avic_access().
 870  */
 871 static bool svm_handle_apic_access(struct registers *guest_regs,
 872                                    struct per_cpu *cpu_data)
 873 {
 874         struct vmcb *vmcb = &cpu_data->vmcb;
 875         struct guest_paging_structures pg_structs;
 876         unsigned int inst_len, offset;
 877         bool is_write;
 878
 879         /* The caller is responsible for sanity checks */
 880         is_write = !!(vmcb->exitinfo1 & 0x2);
 881         offset = vmcb->exitinfo2 - XAPIC_BASE;
 882
 883         if (offset & 0x00f)
 884                 goto out_err;
 885
 886         if (!vcpu_get_guest_paging_structs(&pg_structs))
 887                 goto out_err;
 888
 889         inst_len = apic_mmio_access(guest_regs, cpu_data, vmcb->rip,
 890                                     &pg_structs, offset >> 4, is_write);
 891         if (!inst_len)
 892                 goto out_err;
 893
 894         vcpu_skip_emulated_instruction(inst_len);
 895         return true;
 896
 897 out_err:
 898         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 899                      offset, is_write);
 900         return false;
 901 }
 902
 903 static void dump_guest_regs(struct registers *guest_regs, struct vmcb *vmcb)
 904 {
 905         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 906                      vmcb->rsp, vmcb->rflags);
 907         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 908                      guest_regs->rbx, guest_regs->rcx);
 909         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 910                      guest_regs->rsi, guest_regs->rdi);
 911         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 912                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 913                      !!(vmcb->efer & EFER_LMA));
 914         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 915                      vmcb->cr3, vmcb->cr4);
 916         panic_printk("EFER: %p\n", vmcb->efer);
 917 }
 918
 919 static void svm_get_vcpu_pf_intercept(struct per_cpu *cpu_data,
 920                                       struct vcpu_pf_intercept *out)
 921 {
 922         struct vmcb *vmcb = &cpu_data->vmcb;
 923
 924         out->phys_addr = vmcb->exitinfo2;
 925         out->is_write = !!(vmcb->exitinfo1 & 0x2);
 926 }
 927
 928 static void svm_get_vcpu_io_intercept(struct per_cpu *cpu_data,
 929                                       struct vcpu_io_intercept *out)
 930 {
 931         struct vmcb *vmcb = &cpu_data->vmcb;
 932         u64 exitinfo = vmcb->exitinfo1;
 933
 934         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 935         out->port = (exitinfo >> 16) & 0xFFFF;
 936         out->size = (exitinfo >> 4) & 0x7;
 937         out->in = !!(exitinfo & 0x1);
 938         out->inst_len = vmcb->exitinfo2 - vmcb->rip;
 939         out->rep_or_str = !!(exitinfo & 0x0c);
 940 }
 941
 942 void vcpu_handle_exit(struct registers *guest_regs, struct per_cpu *cpu_data)
 943 {
 944         struct vmcb *vmcb = &cpu_data->vmcb;
 945         struct vcpu_execution_state x_state;
 946         struct vcpu_pf_intercept pf;
 947         struct vcpu_io_intercept io;
 948         bool res = false;
 949         int sipi_vector;
 950
 951         /* Restore GS value expected by per_cpu data accessors */
 952         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 953
 954         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 955         /*
 956          * All guest state is marked unmodified; individual handlers must clear
 957          * the bits as needed.
 958          */
 959         vmcb->clean_bits = 0xffffffff;
 960
 961         switch (vmcb->exitcode) {
 962         case VMEXIT_INVALID:
 963                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 964                              vmcb->exitcode);
 965                 break;
 966         case VMEXIT_NMI:
 967                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 968                 /* Temporarily enable GIF to consume pending NMI */
 969                 asm volatile("stgi; clgi" : : : "memory");
 970                 sipi_vector = x86_handle_events(cpu_data);
 971                 if (sipi_vector >= 0) {
 972                         printk("CPU %d received SIPI, vector %x\n",
 973                                cpu_data->cpu_id, sipi_vector);
 974                         svm_vcpu_reset(cpu_data, sipi_vector);
 975                         vcpu_reset(guest_regs);
 976                 }
 977                 iommu_check_pending_faults(cpu_data);
 978                 return;
 979         case VMEXIT_CPUID:
 980                 /* FIXME: We are not intercepting CPUID now */
 981                 return;
 982         case VMEXIT_VMMCALL:
 983                 vcpu_vendor_get_execution_state(&x_state);
 984                 vcpu_handle_hypercall(guest_regs, &x_state);
 985                 return;
 986         case VMEXIT_CR0_SEL_WRITE:
 987                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 988                 if (svm_handle_cr(guest_regs, cpu_data))
 989                         return;
 990                 break;
 991         case VMEXIT_MSR:
 992                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 993                 if (!vmcb->exitinfo1)
 994                         res = vcpu_handle_msr_read(guest_regs);
 995                 else
 996                         res = svm_handle_msr_write(guest_regs, cpu_data);
 997                 if (res)
 998                         return;
 999                 break;
1000         case VMEXIT_NPF:
1001                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
1002                      vmcb->exitinfo2 >= XAPIC_BASE &&
1003                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
1004                         /* APIC access in non-AVIC mode */
1005                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
1006                         if (svm_handle_apic_access(guest_regs, cpu_data))
1007                                 return;
1008                 } else {
1009                         /* General MMIO (IOAPIC, PCI etc) */
1010                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
1011                         svm_get_vcpu_pf_intercept(cpu_data, &pf);
1012                         if (vcpu_handle_pt_violation(guest_regs, &pf))
1013                                 return;
1014                 }
1015
1016                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
1017                              "error code is %x\n", vmcb->exitinfo2,
1018                              vmcb->exitinfo1 & 0xf);
1019                 break;
1020         case VMEXIT_XSETBV:
1021                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XSETBV]++;
1022                 if ((guest_regs->rax & X86_XCR0_FP) &&
1023                     (guest_regs->rax & ~cpuid_eax(0x0d)) == 0 &&
1024                     guest_regs->rcx == 0 && guest_regs->rdx == 0) {
1025                         vcpu_skip_emulated_instruction(X86_INST_LEN_XSETBV);
1026                         asm volatile(
1027                                 "xsetbv"
1028                                 : /* no output */
1029                                 : "a" (guest_regs->rax), "c" (0), "d" (0));
1030                         return;
1031                 }
1032                 panic_printk("FATAL: Invalid xsetbv parameters: "
1033                              "xcr[%d] = %x:%x\n", guest_regs->rcx,
1034                              guest_regs->rdx, guest_regs->rax);
1035                 break;
1036         case VMEXIT_IOIO:
1037                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
1038                 svm_get_vcpu_io_intercept(cpu_data, &io);
1039                 if (vcpu_handle_io_access(guest_regs, &io))
1040                         return;
1041                 break;
1042         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
1043         default:
1044                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
1045                              "exitinfo1 %p exitinfo2 %p\n",
1046                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
1047         }
1048         dump_guest_regs(guest_regs, vmcb);
1049         panic_park();
1050 }
1051
1052 void vcpu_park(struct per_cpu *cpu_data)
1053 {
1054         struct vmcb *vmcb = &cpu_data->vmcb;
1055
1056         svm_vcpu_reset(cpu_data, APIC_BSP_PSEUDO_SIPI);
1057         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
1058         vmcb->n_cr3 = paging_hvirt2phys(parked_mode_npt);
1059
1060         vcpu_tlb_flush();
1061 }
1062
1063 void vcpu_nmi_handler(void)
1064 {
1065 }
1066
1067 void vcpu_tlb_flush(void)
1068 {
1069         struct per_cpu *cpu_data = this_cpu_data();
1070         struct vmcb *vmcb = &cpu_data->vmcb;
1071
1072         if (has_flush_by_asid)
1073                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1074         else
1075                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1076 }
1077
1078 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1079                               unsigned long pc, unsigned int *size)
1080 {
1081         struct per_cpu *cpu_data = this_cpu_data();
1082         struct vmcb *vmcb = &cpu_data->vmcb;
1083         unsigned long start;
1084
1085         if (has_assists) {
1086                 if (!*size)
1087                         return NULL;
1088                 start = vmcb->rip - pc;
1089                 if (start < vmcb->bytes_fetched) {
1090                         *size = vmcb->bytes_fetched - start;
1091                         return &vmcb->guest_bytes[start];
1092                 } else {
1093                         return NULL;
1094                 }
1095         } else {
1096                 return vcpu_map_inst(pg_structs, pc, size);
1097         }
1098 }
1099
1100 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1101                                     struct vcpu_io_bitmap *iobm)
1102 {
1103         iobm->data = cell->svm.iopm;
1104         iobm->size = sizeof(cell->svm.iopm);
1105 }
1106
1107 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1108 {
1109         struct per_cpu *cpu_data = this_cpu_data();
1110
1111         x_state->efer = cpu_data->vmcb.efer;
1112         x_state->rflags = cpu_data->vmcb.rflags;
1113         x_state->cs = cpu_data->vmcb.cs.selector;
1114         x_state->rip = cpu_data->vmcb.rip;
1115 }
1116
1117 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1118 void enable_irq(void)
1119 {
1120         asm volatile("stgi; sti" : : : "memory");
1121 }
1122
1123 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1124 void disable_irq(void)
1125 {
1126         asm volatile("cli; clgi" : : : "memory");
1127 }