hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell.h>
  19 #include <jailhouse/cell-config.h>
  20 #include <jailhouse/control.h>
  21 #include <jailhouse/paging.h>
  22 #include <jailhouse/printk.h>
  23 #include <jailhouse/processor.h>
  24 #include <jailhouse/string.h>
  25 #include <jailhouse/utils.h>
  26 #include <asm/apic.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 static bool has_avic, has_assists, has_flush_by_asid;
  43
  44 static const struct segment invalid_seg;
  45
  46 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  47
  48 /* bit cleared: direct access allowed */
  49 // TODO: convert to whitelist
  50 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  51         [ SVM_MSRPM_0000 ] = {
  52                 [      0/4 ...  0x017/4 ] = 0,
  53                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  54                 [  0x01c/4 ...  0x1ff/4 ] = 0,
  55                 [  0x200/4 ...  0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
  56                 [  0x274/4 ...  0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
  57                 [  0x278/4 ...  0x2fb/4 ] = 0,
  58                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  59                 [  0x300/4 ...  0x7ff/4 ] = 0,
  60                 /* x2APIC MSRs - emulated if not present */
  61                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  62                 [  0x804/4 ...  0x807/4 ] = 0,
  63                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  64                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  65                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  66                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  67                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  68                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  69                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  70                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  71                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  72                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  73                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  74                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  75                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  76                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  77                 [  0x840/4 ... 0x1fff/4 ] = 0,
  78         },
  79         [ SVM_MSRPM_C000 ] = {
  80                 [      0/4 ...  0x07f/4 ] = 0,
  81                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  82                 [  0x084/4 ... 0x1fff/4 ] = 0
  83         },
  84         [ SVM_MSRPM_C001 ] = {
  85                 [      0/4 ... 0x1fff/4 ] = 0,
  86         },
  87         [ SVM_MSRPM_RESV ] = {
  88                 [      0/4 ... 0x1fff/4 ] = 0,
  89         }
  90 };
  91
  92 /* This page is mapped so the code begins at 0x000ffff0 */
  93 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  94         [0xff0] = 0xfa, /* 1: cli */
  95         [0xff1] = 0xf4, /*    hlt */
  96         [0xff2] = 0xeb,
  97         [0xff3] = 0xfc  /*    jmp 1b */
  98 };
  99
 100 static void *parked_mode_npt;
 101
 102 static void *avic_page;
 103
 104 static int svm_check_features(void)
 105 {
 106         /* SVM is available */
 107         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 108                 return trace_error(-ENODEV);
 109
 110         /* Nested paging */
 111         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 112                 return trace_error(-EIO);
 113
 114         /* Decode assists */
 115         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 116                 has_assists = true;
 117
 118         /* AVIC support */
 119         /* FIXME: Jailhouse support is incomplete so far
 120         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 121                 has_avic = true; */
 122
 123         /* TLB Flush by ASID support */
 124         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 125                 has_flush_by_asid = true;
 126
 127         return 0;
 128 }
 129
 130 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 131                                      const struct desc_table_reg *dtr)
 132 {
 133         svm_segment->base = dtr->base;
 134         svm_segment->limit = dtr->limit & 0xffff;
 135 }
 136
 137 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 138                                          const struct segment *segment)
 139 {
 140         svm_segment->selector = segment->selector;
 141         svm_segment->access_rights = ((segment->access_rights & 0xf000) >> 4) |
 142                 (segment->access_rights & 0x00ff);
 143         svm_segment->limit = segment->limit;
 144         svm_segment->base = segment->base;
 145 }
 146
 147 static void svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 148 {
 149         vmcb->iopm_base_pa = paging_hvirt2phys(cell->arch.svm.iopm);
 150         vmcb->n_cr3 = paging_hvirt2phys(cell->arch.svm.npt_structs.root_table);
 151 }
 152
 153 static void vmcb_setup(struct per_cpu *cpu_data)
 154 {
 155         struct vmcb *vmcb = &cpu_data->vmcb;
 156
 157         memset(vmcb, 0, sizeof(struct vmcb));
 158
 159         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 160         vmcb->cr3 = cpu_data->linux_cr3;
 161         vmcb->cr4 = cpu_data->linux_cr4;
 162
 163         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 164         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 165         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 166         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 167         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 168         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 169         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 170         set_svm_segment_from_segment(&vmcb->ldtr, &invalid_seg);
 171
 172         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 173         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 174
 175         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 176
 177         vmcb->rflags = 0x02;
 178         /* Indicate success to the caller of arch_entry */
 179         vmcb->rax = 0;
 180         vmcb->rsp = cpu_data->linux_sp +
 181                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 182         vmcb->rip = cpu_data->linux_ip;
 183
 184         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 185         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 186         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 187         vmcb->star = read_msr(MSR_STAR);
 188         vmcb->lstar = read_msr(MSR_LSTAR);
 189         vmcb->cstar = read_msr(MSR_CSTAR);
 190         vmcb->sfmask = read_msr(MSR_SFMASK);
 191         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 192
 193         vmcb->dr6 = 0x00000ff0;
 194         vmcb->dr7 = 0x00000400;
 195
 196         /* Make the hypervisor visible */
 197         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 198
 199         vmcb->g_pat = cpu_data->pat;
 200
 201         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 202         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 203         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID;
 204         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 205         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 206         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 207
 208         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 209         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 210
 211         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 212
 213         vmcb->np_enable = 1;
 214         /* No more than one guest owns the CPU */
 215         vmcb->guest_asid = 1;
 216
 217         /* TODO: Setup AVIC */
 218
 219         /* Explicitly mark all of the state as new */
 220         vmcb->clean_bits = 0;
 221
 222         svm_set_cell_config(cpu_data->cell, vmcb);
 223 }
 224
 225 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 226                                      unsigned long gphys,
 227                                      unsigned long flags)
 228 {
 229         return paging_virt2phys(&cpu_data->cell->arch.svm.npt_structs,
 230                         gphys, flags);
 231 }
 232
 233 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 234 {
 235         /* See APMv2, Section 15.25.5 */
 236         *pte = (next_pt & 0x000ffffffffff000UL) |
 237                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 238 }
 239
 240 int vcpu_vendor_init(void)
 241 {
 242         struct paging_structures parking_pt;
 243         unsigned long vm_cr;
 244         int err, n;
 245
 246         err = svm_check_features();
 247         if (err)
 248                 return err;
 249
 250         vm_cr = read_msr(MSR_VM_CR);
 251         if (vm_cr & VM_CR_SVMDIS)
 252                 /* SVM disabled in BIOS */
 253                 return trace_error(-EPERM);
 254
 255         /* Nested paging is the same as the native one */
 256         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 257         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 258                 npt_paging[n].set_next_pt = npt_set_next_pt;
 259
 260         /* Map guest parking code (shared between cells and CPUs) */
 261         parking_pt.root_paging = npt_paging;
 262         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 263         if (!parked_mode_npt)
 264                 return -ENOMEM;
 265         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 266                             PAGE_SIZE, 0x000ff000,
 267                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 268                             PAGING_NON_COHERENT);
 269         if (err)
 270                 return err;
 271
 272         /* This is always false for AMD now (except in nested SVM);
 273            see Sect. 16.3.1 in APMv2 */
 274         if (using_x2apic) {
 275                 /* allow direct x2APIC access except for ICR writes */
 276                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 277                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 278                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 279         } else {
 280                 if (has_avic) {
 281                         avic_page = page_alloc(&remap_pool, 1);
 282                         if (!avic_page)
 283                                 return trace_error(-ENOMEM);
 284                 }
 285         }
 286
 287         return vcpu_cell_init(&root_cell);
 288 }
 289
 290 int vcpu_vendor_cell_init(struct cell *cell)
 291 {
 292         int err = -ENOMEM;
 293         u64 flags;
 294
 295         /* allocate iopm (two 4-K pages + 3 bits) */
 296         cell->arch.svm.iopm = page_alloc(&mem_pool, 3);
 297         if (!cell->arch.svm.iopm)
 298                 return err;
 299
 300         /* build root NPT of cell */
 301         cell->arch.svm.npt_structs.root_paging = npt_paging;
 302         cell->arch.svm.npt_structs.root_table =
 303                 (page_table_t)cell->arch.root_table_page;
 304
 305         if (!has_avic) {
 306                 /*
 307                  * Map xAPIC as is; reads are passed, writes are trapped.
 308                  */
 309                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 310                 err = paging_create(&cell->arch.svm.npt_structs, XAPIC_BASE,
 311                                     PAGE_SIZE, XAPIC_BASE,
 312                                     flags,
 313                                     PAGING_NON_COHERENT);
 314         } else {
 315                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 316                 err = paging_create(&cell->arch.svm.npt_structs,
 317                                     paging_hvirt2phys(avic_page),
 318                                     PAGE_SIZE, XAPIC_BASE,
 319                                     flags,
 320                                     PAGING_NON_COHERENT);
 321         }
 322         if (err)
 323                 goto err_free_iopm;
 324
 325         return 0;
 326
 327 err_free_iopm:
 328         page_free(&mem_pool, cell->arch.svm.iopm, 3);
 329
 330         return err;
 331 }
 332
 333 int vcpu_map_memory_region(struct cell *cell,
 334                            const struct jailhouse_memory *mem)
 335 {
 336         u64 phys_start = mem->phys_start;
 337         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 338
 339         if (mem->flags & JAILHOUSE_MEM_READ)
 340                 flags |= PAGE_FLAG_PRESENT;
 341         if (mem->flags & JAILHOUSE_MEM_WRITE)
 342                 flags |= PAGE_FLAG_RW;
 343         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 344                 flags |= PAGE_FLAG_NOEXECUTE;
 345         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 346                 phys_start = paging_hvirt2phys(&cell->comm_page);
 347
 348         return paging_create(&cell->arch.svm.npt_structs, phys_start, mem->size,
 349                              mem->virt_start, flags, PAGING_NON_COHERENT);
 350 }
 351
 352 int vcpu_unmap_memory_region(struct cell *cell,
 353                              const struct jailhouse_memory *mem)
 354 {
 355         return paging_destroy(&cell->arch.svm.npt_structs, mem->virt_start,
 356                               mem->size, PAGING_NON_COHERENT);
 357 }
 358
 359 void vcpu_vendor_cell_exit(struct cell *cell)
 360 {
 361         paging_destroy(&cell->arch.svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 362                        PAGING_NON_COHERENT);
 363         page_free(&mem_pool, cell->arch.svm.iopm, 3);
 364 }
 365
 366 int vcpu_init(struct per_cpu *cpu_data)
 367 {
 368         unsigned long efer;
 369         int err;
 370
 371         err = svm_check_features();
 372         if (err)
 373                 return err;
 374
 375         efer = read_msr(MSR_EFER);
 376         if (efer & EFER_SVME)
 377                 return trace_error(-EBUSY);
 378
 379         efer |= EFER_SVME;
 380         write_msr(MSR_EFER, efer);
 381
 382         cpu_data->svm_state = SVMON;
 383
 384         vmcb_setup(cpu_data);
 385
 386         /*
 387          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 388          * set the values of reserved bits to the values found during the
 389          * previous CR0 read."
 390          * But we want to avoid surprises with new features unknown to us but
 391          * set by Linux. So check if any assumed revered bit was set and bail
 392          * out if so.
 393          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 394          */
 395         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 396                 return -EIO;
 397
 398         /* bring CR0 and CR4 into well-defined states */
 399         write_cr0(X86_CR0_HOST_STATE);
 400         write_cr4(X86_CR4_HOST_STATE);
 401
 402         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 403
 404         return 0;
 405 }
 406
 407 void vcpu_exit(struct per_cpu *cpu_data)
 408 {
 409         unsigned long efer;
 410
 411         if (cpu_data->svm_state == SVMOFF)
 412                 return;
 413
 414         cpu_data->svm_state = SVMOFF;
 415
 416         /* We are leaving - set the GIF */
 417         asm volatile ("stgi" : : : "memory");
 418
 419         efer = read_msr(MSR_EFER);
 420         efer &= ~EFER_SVME;
 421         write_msr(MSR_EFER, efer);
 422
 423         write_msr(MSR_VM_HSAVE_PA, 0);
 424 }
 425
 426 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 427 {
 428         unsigned long vmcb_pa, host_stack;
 429
 430         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 431         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 432
 433         /* We enter Linux at the point arch_entry would return to as well.
 434          * rax is cleared to signal success to the caller. */
 435         asm volatile(
 436                 "clgi\n\t"
 437                 "mov (%%rdi),%%r15\n\t"
 438                 "mov 0x8(%%rdi),%%r14\n\t"
 439                 "mov 0x10(%%rdi),%%r13\n\t"
 440                 "mov 0x18(%%rdi),%%r12\n\t"
 441                 "mov 0x20(%%rdi),%%rbx\n\t"
 442                 "mov 0x28(%%rdi),%%rbp\n\t"
 443                 "mov %2,%%rsp\n\t"
 444                 "vmload %%rax\n\t"
 445                 "jmp svm_vmentry"
 446                 : /* no output */
 447                 : "D" (cpu_data->linux_reg), "a" (vmcb_pa), "m" (host_stack));
 448         __builtin_unreachable();
 449 }
 450
 451 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
 452 {
 453         struct per_cpu *cpu_data = this_cpu_data();
 454         struct vmcb *vmcb = &cpu_data->vmcb;
 455         unsigned long *stack = (unsigned long *)vmcb->rsp;
 456         unsigned long linux_ip = vmcb->rip;
 457
 458         cpu_data->linux_cr0 = vmcb->cr0;
 459         cpu_data->linux_cr3 = vmcb->cr3;
 460
 461         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 462         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 463         cpu_data->linux_idtr.base = vmcb->idtr.base;
 464         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 465
 466         cpu_data->linux_cs.selector = vmcb->cs.selector;
 467
 468         asm volatile("str %0" : "=m" (cpu_data->linux_tss.selector));
 469
 470         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 471         cpu_data->linux_fs.base = read_msr(MSR_FS_BASE);
 472         cpu_data->linux_gs.base = vmcb->gs.base;
 473
 474         cpu_data->linux_ds.selector = vmcb->ds.selector;
 475         cpu_data->linux_es.selector = vmcb->es.selector;
 476
 477         asm volatile("mov %%fs,%0" : "=m" (cpu_data->linux_fs.selector));
 478         asm volatile("mov %%gs,%0" : "=m" (cpu_data->linux_gs.selector));
 479
 480         arch_cpu_restore(cpu_data, 0);
 481
 482         stack--;
 483         *stack = linux_ip;
 484
 485         asm volatile (
 486                 "mov %%rbx,%%rsp\n\t"
 487                 "pop %%r15\n\t"
 488                 "pop %%r14\n\t"
 489                 "pop %%r13\n\t"
 490                 "pop %%r12\n\t"
 491                 "pop %%r11\n\t"
 492                 "pop %%r10\n\t"
 493                 "pop %%r9\n\t"
 494                 "pop %%r8\n\t"
 495                 "pop %%rdi\n\t"
 496                 "pop %%rsi\n\t"
 497                 "pop %%rbp\n\t"
 498                 "add $8,%%rsp\n\t"
 499                 "pop %%rbx\n\t"
 500                 "pop %%rdx\n\t"
 501                 "pop %%rcx\n\t"
 502                 "mov %%rax,%%rsp\n\t"
 503                 "xor %%rax,%%rax\n\t"
 504                 "ret"
 505                 : : "a" (stack), "b" (&cpu_data->guest_regs));
 506         __builtin_unreachable();
 507 }
 508
 509 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 510 {
 511         static const struct svm_segment dataseg_reset_state = {
 512                 .selector = 0,
 513                 .base = 0,
 514                 .limit = 0xffff,
 515                 .access_rights = 0x0093,
 516         };
 517         static const struct svm_segment dtr_reset_state = {
 518                 .selector = 0,
 519                 .base = 0,
 520                 .limit = 0xffff,
 521                 .access_rights = 0,
 522         };
 523         struct vmcb *vmcb = &cpu_data->vmcb;
 524         unsigned long val;
 525
 526         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 527         vmcb->cr3 = 0;
 528         vmcb->cr4 = 0;
 529
 530         vmcb->rflags = 0x02;
 531
 532         val = 0;
 533         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 534                 val = 0xfff0;
 535                 sipi_vector = 0xf0;
 536         }
 537         vmcb->rip = val;
 538         vmcb->rsp = 0;
 539
 540         vmcb->cs.selector = sipi_vector << 8;
 541         vmcb->cs.base = sipi_vector << 12;
 542         vmcb->cs.limit = 0xffff;
 543         vmcb->cs.access_rights = 0x009b;
 544
 545         vmcb->ds = dataseg_reset_state;
 546         vmcb->es = dataseg_reset_state;
 547         vmcb->fs = dataseg_reset_state;
 548         vmcb->gs = dataseg_reset_state;
 549         vmcb->ss = dataseg_reset_state;
 550
 551         vmcb->tr.selector = 0;
 552         vmcb->tr.base = 0;
 553         vmcb->tr.limit = 0xffff;
 554         vmcb->tr.access_rights = 0x008b;
 555
 556         vmcb->ldtr.selector = 0;
 557         vmcb->ldtr.base = 0;
 558         vmcb->ldtr.limit = 0xffff;
 559         vmcb->ldtr.access_rights = 0x0082;
 560
 561         vmcb->gdtr = dtr_reset_state;
 562         vmcb->idtr = dtr_reset_state;
 563
 564         vmcb->efer = EFER_SVME;
 565
 566         /* These MSRs are undefined on reset */
 567         vmcb->star = 0;
 568         vmcb->lstar = 0;
 569         vmcb->cstar = 0;
 570         vmcb->sfmask = 0;
 571         vmcb->sysenter_cs = 0;
 572         vmcb->sysenter_eip = 0;
 573         vmcb->sysenter_esp = 0;
 574         vmcb->kerngsbase = 0;
 575
 576         vmcb->dr7 = 0x00000400;
 577
 578         /* Almost all of the guest state changed */
 579         vmcb->clean_bits = 0;
 580
 581         svm_set_cell_config(cpu_data->cell, vmcb);
 582
 583         asm volatile(
 584                 "vmload %%rax"
 585                 : : "a" (paging_hvirt2phys(vmcb)) : "memory");
 586         /* vmload overwrites GS_BASE - restore the host state */
 587         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 588 }
 589
 590 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 591 {
 592         this_cpu_data()->vmcb.rip += inst_len;
 593 }
 594
 595 static void update_efer(struct vmcb *vmcb)
 596 {
 597         unsigned long efer = vmcb->efer;
 598
 599         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 600                 return;
 601
 602         efer |= EFER_LMA;
 603
 604         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 605         if ((vmcb->efer ^ efer) & EFER_LMA)
 606                 vcpu_tlb_flush();
 607
 608         vmcb->efer = efer;
 609         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 610 }
 611
 612 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 613 {
 614         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 615
 616         if (vmcb->efer & EFER_LMA) {
 617                 pg_structs->root_paging = x86_64_paging;
 618                 pg_structs->root_table_gphys =
 619                         vmcb->cr3 & 0x000ffffffffff000UL;
 620         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 621                    !(vmcb->cr4 & X86_CR4_PAE)) {
 622                 pg_structs->root_paging = i386_paging;
 623                 pg_structs->root_table_gphys =
 624                         vmcb->cr3 & 0xfffff000UL;
 625         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 626                 /*
 627                  * Can be in non-paged protected mode as well, but
 628                  * the translation mechanism will stay the same ayway.
 629                  */
 630                 pg_structs->root_paging = realmode_paging;
 631                 /*
 632                  * This will make paging_get_guest_pages map the page
 633                  * that also contains the bootstrap code and, thus, is
 634                  * always present in a cell.
 635                  */
 636                 pg_structs->root_table_gphys = 0xff000;
 637         } else {
 638                 printk("FATAL: Unsupported paging mode\n");
 639                 return false;
 640         }
 641         return true;
 642 }
 643
 644 void vcpu_vendor_set_guest_pat(unsigned long val)
 645 {
 646         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 647
 648         vmcb->g_pat = val;
 649         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 650 }
 651
 652 struct parse_context {
 653         unsigned int remaining;
 654         unsigned int size;
 655         unsigned long cs_base;
 656         const u8 *inst;
 657 };
 658
 659 static bool ctx_advance(struct parse_context *ctx,
 660                         unsigned long *pc,
 661                         struct guest_paging_structures *pg_structs)
 662 {
 663         if (!ctx->size) {
 664                 ctx->size = ctx->remaining;
 665                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 666                                           &ctx->size);
 667                 if (!ctx->inst)
 668                         return false;
 669                 ctx->remaining -= ctx->size;
 670                 *pc += ctx->size;
 671         }
 672         return true;
 673 }
 674
 675 static bool svm_parse_mov_to_cr(struct vmcb *vmcb, unsigned long pc,
 676                                 unsigned char reg, unsigned long *gpr)
 677 {
 678         struct guest_paging_structures pg_structs;
 679         struct parse_context ctx = {};
 680         /* No prefixes are supported yet */
 681         u8 opcodes[] = {0x0f, 0x22}, modrm;
 682         int n;
 683
 684         ctx.remaining = ARRAY_SIZE(opcodes);
 685         if (!vcpu_get_guest_paging_structs(&pg_structs))
 686                 return false;
 687         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 688
 689         if (!ctx_advance(&ctx, &pc, &pg_structs))
 690                 return false;
 691
 692         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++)
 693                 if (*(ctx.inst) != opcodes[n] ||
 694                     !ctx_advance(&ctx, &pc, &pg_structs))
 695                         return false;
 696
 697         if (!ctx_advance(&ctx, &pc, &pg_structs))
 698                 return false;
 699
 700         modrm = *(ctx.inst);
 701
 702         if (((modrm & 0x38) >> 3) != reg)
 703                 return false;
 704
 705         if (gpr)
 706                 *gpr = (modrm & 0x7);
 707
 708         return true;
 709 }
 710
 711 /*
 712  * XXX: The only visible reason to have this function (vmx.c consistency
 713  * aside) is to prevent cells from setting invalid CD+NW combinations that
 714  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 715  * altogether?
 716  */
 717 static bool svm_handle_cr(struct per_cpu *cpu_data)
 718 {
 719         struct vmcb *vmcb = &cpu_data->vmcb;
 720         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 721         unsigned long reg = -1, val, bits;
 722
 723         if (has_assists) {
 724                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 725                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 726                         return false;
 727                 }
 728                 reg = vmcb->exitinfo1 & 0x07;
 729         } else {
 730                 if (!svm_parse_mov_to_cr(vmcb, vmcb->rip, 0, &reg)) {
 731                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 732                         return false;
 733                 }
 734         }
 735
 736         if (reg == 4)
 737                 val = vmcb->rsp;
 738         else
 739                 val = cpu_data->guest_regs.by_index[15 - reg];
 740
 741         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 742         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 743         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 744         if ((val ^ vmcb->cr0) & bits)
 745                 vcpu_tlb_flush();
 746         /* TODO: better check for #GP reasons */
 747         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 748         if (val & X86_CR0_PG)
 749                 update_efer(vmcb);
 750         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 751
 752         return true;
 753 }
 754
 755 static bool svm_handle_msr_write(struct per_cpu *cpu_data)
 756 {
 757         struct vmcb *vmcb = &cpu_data->vmcb;
 758         unsigned long efer;
 759
 760         if (cpu_data->guest_regs.rcx == MSR_EFER) {
 761                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 762                 efer = get_wrmsr_value(&cpu_data->guest_regs) | EFER_SVME;
 763                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 764                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 765                         vcpu_tlb_flush();
 766                 vmcb->efer = efer;
 767                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 768                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 769                 return true;
 770         }
 771
 772         return vcpu_handle_msr_write();
 773 }
 774
 775 /*
 776  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 777  * be treated separately in svm_handle_avic_access().
 778  */
 779 static bool svm_handle_apic_access(struct vmcb *vmcb)
 780 {
 781         struct guest_paging_structures pg_structs;
 782         unsigned int inst_len, offset;
 783         bool is_write;
 784
 785         /* The caller is responsible for sanity checks */
 786         is_write = !!(vmcb->exitinfo1 & 0x2);
 787         offset = vmcb->exitinfo2 - XAPIC_BASE;
 788
 789         if (offset & 0x00f)
 790                 goto out_err;
 791
 792         if (!vcpu_get_guest_paging_structs(&pg_structs))
 793                 goto out_err;
 794
 795         inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
 796                                     is_write);
 797         if (!inst_len)
 798                 goto out_err;
 799
 800         vcpu_skip_emulated_instruction(inst_len);
 801         return true;
 802
 803 out_err:
 804         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 805                      offset, is_write);
 806         return false;
 807 }
 808
 809 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
 810 {
 811         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 812                      vmcb->rsp, vmcb->rflags);
 813         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 814                      guest_regs->rbx, guest_regs->rcx);
 815         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 816                      guest_regs->rsi, guest_regs->rdi);
 817         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 818                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 819                      !!(vmcb->efer & EFER_LMA));
 820         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 821                      vmcb->cr3, vmcb->cr4);
 822         panic_printk("EFER: %p\n", vmcb->efer);
 823 }
 824
 825 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
 826 {
 827         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 828         u64 exitinfo = vmcb->exitinfo1;
 829
 830         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 831         io->port = (exitinfo >> 16) & 0xFFFF;
 832         io->size = (exitinfo >> 4) & 0x7;
 833         io->in = !!(exitinfo & 0x1);
 834         io->inst_len = vmcb->exitinfo2 - vmcb->rip;
 835         io->rep_or_str = !!(exitinfo & 0x0c);
 836 }
 837
 838 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
 839 {
 840         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 841
 842         mmio->phys_addr = vmcb->exitinfo2;
 843         mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
 844 }
 845
 846 void vcpu_handle_exit(struct per_cpu *cpu_data)
 847 {
 848         struct vmcb *vmcb = &cpu_data->vmcb;
 849         bool res = false;
 850         int sipi_vector;
 851
 852         vmcb->gs.base = read_msr(MSR_GS_BASE);
 853
 854         /* Restore GS value expected by per_cpu data accessors */
 855         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 856
 857         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 858         /*
 859          * All guest state is marked unmodified; individual handlers must clear
 860          * the bits as needed.
 861          */
 862         vmcb->clean_bits = 0xffffffff;
 863
 864         switch (vmcb->exitcode) {
 865         case VMEXIT_INVALID:
 866                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 867                              vmcb->exitcode);
 868                 break;
 869         case VMEXIT_NMI:
 870                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 871                 /* Temporarily enable GIF to consume pending NMI */
 872                 asm volatile("stgi; clgi" : : : "memory");
 873                 sipi_vector = x86_handle_events(cpu_data);
 874                 if (sipi_vector >= 0) {
 875                         printk("CPU %d received SIPI, vector %x\n",
 876                                cpu_data->cpu_id, sipi_vector);
 877                         svm_vcpu_reset(cpu_data, sipi_vector);
 878                         vcpu_reset(sipi_vector == APIC_BSP_PSEUDO_SIPI);
 879                 }
 880                 iommu_check_pending_faults();
 881                 goto vmentry;
 882         case VMEXIT_VMMCALL:
 883                 vcpu_handle_hypercall();
 884                 goto vmentry;
 885         case VMEXIT_CR0_SEL_WRITE:
 886                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 887                 if (svm_handle_cr(cpu_data))
 888                         goto vmentry;
 889                 break;
 890         case VMEXIT_CPUID:
 891                 vcpu_handle_cpuid();
 892                 goto vmentry;
 893         case VMEXIT_MSR:
 894                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 895                 if (!vmcb->exitinfo1)
 896                         res = vcpu_handle_msr_read();
 897                 else
 898                         res = svm_handle_msr_write(cpu_data);
 899                 if (res)
 900                         goto vmentry;
 901                 break;
 902         case VMEXIT_NPF:
 903                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
 904                      vmcb->exitinfo2 >= XAPIC_BASE &&
 905                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
 906                         /* APIC access in non-AVIC mode */
 907                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
 908                         if (svm_handle_apic_access(vmcb))
 909                                 goto vmentry;
 910                 } else {
 911                         /* General MMIO (IOAPIC, PCI etc) */
 912                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
 913                         if (vcpu_handle_mmio_access())
 914                                 goto vmentry;
 915                 }
 916                 break;
 917         case VMEXIT_XSETBV:
 918                 if (vcpu_handle_xsetbv())
 919                         goto vmentry;
 920                 break;
 921         case VMEXIT_IOIO:
 922                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
 923                 if (vcpu_handle_io_access())
 924                         goto vmentry;
 925                 break;
 926         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
 927         default:
 928                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
 929                              "exitinfo1 %p exitinfo2 %p\n",
 930                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
 931         }
 932         dump_guest_regs(&cpu_data->guest_regs, vmcb);
 933         panic_park();
 934
 935 vmentry:
 936         write_msr(MSR_GS_BASE, vmcb->gs.base);
 937 }
 938
 939 void vcpu_park(void)
 940 {
 941         svm_vcpu_reset(this_cpu_data(), APIC_BSP_PSEUDO_SIPI);
 942         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
 943         this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
 944
 945         vcpu_tlb_flush();
 946 }
 947
 948 void vcpu_nmi_handler(void)
 949 {
 950 }
 951
 952 void vcpu_tlb_flush(void)
 953 {
 954         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 955
 956         if (has_flush_by_asid)
 957                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
 958         else
 959                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
 960 }
 961
 962 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
 963                               unsigned long pc, unsigned int *size)
 964 {
 965         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 966         unsigned long start;
 967
 968         if (has_assists) {
 969                 if (!*size)
 970                         return NULL;
 971                 start = vmcb->rip - pc;
 972                 if (start < vmcb->bytes_fetched) {
 973                         *size = vmcb->bytes_fetched - start;
 974                         return &vmcb->guest_bytes[start];
 975                 } else {
 976                         return NULL;
 977                 }
 978         } else {
 979                 return vcpu_map_inst(pg_structs, pc, size);
 980         }
 981 }
 982
 983 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
 984                                     struct vcpu_io_bitmap *iobm)
 985 {
 986         iobm->data = cell->arch.svm.iopm;
 987         iobm->size = sizeof(cell->arch.svm.iopm);
 988 }
 989
 990 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
 991 {
 992         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 993
 994         x_state->efer = vmcb->efer;
 995         x_state->rflags = vmcb->rflags;
 996         x_state->cs = vmcb->cs.selector;
 997         x_state->rip = vmcb->rip;
 998 }
 999
1000 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1001 void enable_irq(void)
1002 {
1003         asm volatile("stgi; sti" : : : "memory");
1004 }
1005
1006 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1007 void disable_irq(void)
1008 {
1009         asm volatile("cli; clgi" : : : "memory");
1010 }