hypervisor/arch/x86/dbg-write.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include <jailhouse/printk.h>
  14 #include <jailhouse/processor.h>
  15 #include <asm/io.h>
  16
  17 #ifdef CONFIG_UART_OXPCIE952
  18 #define UART_BASE               0xe010
  19 #else
  20 #define UART_BASE               0x3f8
  21 #endif
  22 #define  UART_TX                0x0
  23 #define  UART_DLL               0x0
  24 #define  UART_DLM               0x1
  25 #define  UART_LCR               0x3
  26 #define  UART_LCR_8N1           0x03
  27 #define  UART_LCR_DLAB          0x80
  28 #define  UART_LSR               0x5
  29 #define  UART_LSR_THRE          0x20
  30
  31 void arch_dbg_write_init(void)
  32 {
  33         outb(UART_LCR_DLAB, UART_BASE + UART_LCR);
  34 #ifdef CONFIG_UART_OXPCIE952
  35         outb(0x22, UART_BASE + UART_DLL);
  36 #else
  37         outb(1, UART_BASE + UART_DLL);
  38 #endif
  39         outb(0, UART_BASE + UART_DLM);
  40         outb(UART_LCR_8N1, UART_BASE + UART_LCR);
  41 }
  42
  43 void arch_dbg_write(const char *msg)
  44 {
  45         char c;
  46
  47         while (1) {
  48                 c = *msg++;
  49                 if (!c)
  50                         break;
  51                 while (!(inb(UART_BASE + UART_LSR) & UART_LSR_THRE))
  52                         cpu_relax();
  53                 if (panic_in_progress && panic_cpu != phys_processor_id())
  54                         break;
  55                 outb(c, UART_BASE + UART_TX);
  56         }
  57 }