hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_CLEARED_BITS    ~X86_CR0_NW
  41
  42 #define MTRR_DEFTYPE            0x2ff
  43
  44 #define PAT_RESET_VALUE         0x0007040600070406UL
  45
  46 static bool has_avic, has_assists, has_flush_by_asid;
  47
  48 static const struct segment invalid_seg;
  49
  50 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  51
  52 /* bit cleared: direct access allowed */
  53 // TODO: convert to whitelist
  54 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  55         [ SVM_MSRPM_0000 ] = {
  56                 [      0/4 ...  0x017/4 ] = 0,
  57                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  58                 [  0x01c/4 ...  0x2fb/4 ] = 0,
  59                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  60                 [  0x300/4 ...  0x7ff/4 ] = 0,
  61                 /* x2APIC MSRs - emulated if not present */
  62                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  63                 [  0x804/4 ...  0x807/4 ] = 0,
  64                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  65                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  66                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  67                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  68                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  69                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  70                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  71                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  72                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  73                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  74                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  75                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  76                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  77                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  78                 [  0x840/4 ... 0x1fff/4 ] = 0,
  79         },
  80         [ SVM_MSRPM_C000 ] = {
  81                 [      0/4 ...  0x07f/4 ] = 0,
  82                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  83                 [  0x084/4 ... 0x1fff/4 ] = 0
  84         },
  85         [ SVM_MSRPM_C001 ] = {
  86                 [      0/4 ... 0x1fff/4 ] = 0,
  87         },
  88         [ SVM_MSRPM_RESV ] = {
  89                 [      0/4 ... 0x1fff/4 ] = 0,
  90         }
  91 };
  92
  93 /* This page is mapped so the code begins at 0x000ffff0 */
  94 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  95         [0xff0] = 0xfa, /* 1: cli */
  96         [0xff1] = 0xf4, /*    hlt */
  97         [0xff2] = 0xeb,
  98         [0xff3] = 0xfc  /*    jmp 1b */
  99 };
 100
 101 static void *parked_mode_npt;
 102
 103 static void *avic_page;
 104
 105 static int svm_check_features(void)
 106 {
 107         /* SVM is available */
 108         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 109                 return -ENODEV;
 110
 111         /* Nested paging */
 112         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 113                 return -EIO;
 114
 115         /* Decode assists */
 116         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 117                 has_assists = true;
 118
 119         /* AVIC support */
 120         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 121                 has_avic = true;
 122
 123         /* TLB Flush by ASID support */
 124         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 125                 has_flush_by_asid = true;
 126
 127         return 0;
 128 }
 129
 130 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 131                                      const struct desc_table_reg *dtr)
 132 {
 133         struct svm_segment tmp = { 0 };
 134
 135         if (dtr) {
 136                 tmp.base = dtr->base;
 137                 tmp.limit = dtr->limit & 0xffff;
 138         }
 139
 140         *svm_segment = tmp;
 141 }
 142
 143 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
 144 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 145                                          const struct segment *segment)
 146 {
 147         u32 ar;
 148
 149         svm_segment->selector = segment->selector;
 150
 151         if (segment->access_rights == 0x10000) {
 152                 svm_segment->access_rights = 0;
 153         } else {
 154                 ar = segment->access_rights;
 155                 svm_segment->access_rights =
 156                         ((ar & 0xf000) >> 4) | (ar & 0x00ff);
 157         }
 158
 159         svm_segment->limit = segment->limit;
 160         svm_segment->base = segment->base;
 161 }
 162
 163 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 164 {
 165         /* No real need for this function; used for consistency with vmx.c */
 166         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 167         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 168
 169         return true;
 170 }
 171
 172 static int vmcb_setup(struct per_cpu *cpu_data)
 173 {
 174         struct vmcb *vmcb = &cpu_data->vmcb;
 175
 176         memset(vmcb, 0, sizeof(struct vmcb));
 177
 178         vmcb->cr0 = read_cr0() & SVM_CR0_CLEARED_BITS;
 179         vmcb->cr3 = cpu_data->linux_cr3;
 180         vmcb->cr4 = read_cr4();
 181
 182         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 183         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 184         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 185         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 186         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 187         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 188         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 189
 190         set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
 191         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 192         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 193
 194         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 195
 196         vmcb->rflags = 0x02;
 197         /* Indicate success to the caller of arch_entry */
 198         vmcb->rax = 0;
 199         vmcb->rsp = cpu_data->linux_sp +
 200                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 201         vmcb->rip = cpu_data->linux_ip;
 202
 203         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 204         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 205         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 206         vmcb->star = read_msr(MSR_STAR);
 207         vmcb->lstar = read_msr(MSR_LSTAR);
 208         vmcb->cstar = read_msr(MSR_CSTAR);
 209         vmcb->sfmask = read_msr(MSR_SFMASK);
 210         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 211
 212         vmcb->dr6 = 0x00000ff0;
 213         vmcb->dr7 = 0x00000400;
 214
 215         /* Make the hypervisor visible */
 216         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 217
 218         /* Linux uses custom PAT setting */
 219         vmcb->g_pat = read_msr(MSR_IA32_PAT);
 220
 221         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 222         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 223         /* TODO: Do we need this for SVM ? */
 224         /* vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID; */
 225         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 226         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 227         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 228
 229         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 230         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 231
 232         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 233
 234         vmcb->np_enable = 1;
 235         /* No more than one guest owns the CPU */
 236         vmcb->guest_asid = 1;
 237
 238         /* TODO: Setup AVIC */
 239
 240         /* Explicitly mark all of the state as new */
 241         vmcb->clean_bits = 0;
 242
 243         return svm_set_cell_config(cpu_data->cell, vmcb);
 244 }
 245
 246 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 247                                      unsigned long gphys,
 248                                      unsigned long flags)
 249 {
 250         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 251                         gphys, flags);
 252 }
 253
 254 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 255 {
 256         /* See APMv2, Section 15.25.5 */
 257         *pte = (next_pt & 0x000ffffffffff000UL) |
 258                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 259 }
 260
 261 int vcpu_vendor_init(void)
 262 {
 263         struct paging_structures parking_pt;
 264         unsigned long vm_cr;
 265         int err, n;
 266
 267         err = svm_check_features();
 268         if (err)
 269                 return err;
 270
 271         vm_cr = read_msr(MSR_VM_CR);
 272         if (vm_cr & VM_CR_SVMDIS)
 273                 /* SVM disabled in BIOS */
 274                 return -EPERM;
 275
 276         /* Nested paging is the same as the native one */
 277         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 278         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 279                 npt_paging[n].set_next_pt = npt_set_next_pt;
 280
 281         /* Map guest parking code (shared between cells and CPUs) */
 282         parking_pt.root_paging = npt_paging;
 283         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 284         if (!parked_mode_npt)
 285                 return -ENOMEM;
 286         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 287                             PAGE_SIZE, 0x000ff000,
 288                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 289                             PAGING_NON_COHERENT);
 290         if (err)
 291                 return err;
 292
 293         /* This is always false for AMD now (except in nested SVM);
 294            see Sect. 16.3.1 in APMv2 */
 295         if (using_x2apic) {
 296                 /* allow direct x2APIC access except for ICR writes */
 297                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 298                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 299                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 300         } else {
 301                 if (has_avic) {
 302                         avic_page = page_alloc(&remap_pool, 1);
 303                         if (!avic_page)
 304                                 return -ENOMEM;
 305                 }
 306         }
 307
 308         return vcpu_cell_init(&root_cell);
 309 }
 310
 311 int vcpu_vendor_cell_init(struct cell *cell)
 312 {
 313         u64 flags;
 314         int err;
 315
 316         /* allocate iopm (two 4-K pages + 3 bits) */
 317         cell->svm.iopm = page_alloc(&mem_pool, 3);
 318         if (!cell->svm.iopm)
 319                 return -ENOMEM;
 320
 321         /* build root NPT of cell */
 322         cell->svm.npt_structs.root_paging = npt_paging;
 323         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 324         if (!cell->svm.npt_structs.root_table)
 325                 return -ENOMEM;
 326
 327         if (!has_avic) {
 328                 /*
 329                  * Map xAPIC as is; reads are passed, writes are trapped.
 330                  */
 331                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 332                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 333                                     PAGE_SIZE, XAPIC_BASE,
 334                                     flags,
 335                                     PAGING_NON_COHERENT);
 336         } else {
 337                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 338                 err = paging_create(&cell->svm.npt_structs,
 339                                     paging_hvirt2phys(avic_page),
 340                                     PAGE_SIZE, XAPIC_BASE,
 341                                     flags,
 342                                     PAGING_NON_COHERENT);
 343         }
 344
 345         return err;
 346 }
 347
 348 int vcpu_map_memory_region(struct cell *cell,
 349                            const struct jailhouse_memory *mem)
 350 {
 351         u64 phys_start = mem->phys_start;
 352         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 353
 354         if (mem->flags & JAILHOUSE_MEM_READ)
 355                 flags |= PAGE_FLAG_PRESENT;
 356         if (mem->flags & JAILHOUSE_MEM_WRITE)
 357                 flags |= PAGE_FLAG_RW;
 358         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 359                 flags |= PAGE_FLAG_NOEXECUTE;
 360         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 361                 phys_start = paging_hvirt2phys(&cell->comm_page);
 362
 363         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 364                              mem->virt_start, flags, PAGING_NON_COHERENT);
 365 }
 366
 367 int vcpu_unmap_memory_region(struct cell *cell,
 368                              const struct jailhouse_memory *mem)
 369 {
 370         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 371                               mem->size, PAGING_NON_COHERENT);
 372 }
 373
 374 void vcpu_vendor_cell_exit(struct cell *cell)
 375 {
 376         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 377                        PAGING_NON_COHERENT);
 378         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 379 }
 380
 381 int vcpu_init(struct per_cpu *cpu_data)
 382 {
 383         unsigned long efer;
 384         int err;
 385
 386         err = svm_check_features();
 387         if (err)
 388                 return err;
 389
 390         efer = read_msr(MSR_EFER);
 391         if (efer & EFER_SVME)
 392                 return -EBUSY;
 393
 394         efer |= EFER_SVME;
 395         write_msr(MSR_EFER, efer);
 396
 397         cpu_data->svm_state = SVMON;
 398
 399         if (!vmcb_setup(cpu_data))
 400                 return -EIO;
 401
 402         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 403
 404         return 0;
 405 }
 406
 407 void vcpu_exit(struct per_cpu *cpu_data)
 408 {
 409         unsigned long efer;
 410
 411         if (cpu_data->svm_state == SVMOFF)
 412                 return;
 413
 414         cpu_data->svm_state = SVMOFF;
 415
 416         /* We are leaving - set the GIF */
 417         asm volatile ("stgi" : : : "memory");
 418
 419         efer = read_msr(MSR_EFER);
 420         efer &= ~EFER_SVME;
 421         write_msr(MSR_EFER, efer);
 422
 423         write_msr(MSR_VM_HSAVE_PA, 0);
 424 }
 425
 426 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 427 {
 428         unsigned long vmcb_pa, host_stack;
 429
 430         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 431         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 432
 433         /*
 434          * XXX: Jailhouse doesn't use PAT, so it is explicitly set to the
 435          * reset value. However, this value is later combined with vmcb->g_pat
 436          * (as per APMv2, Sect. 15.25.8) which may lead to subtle bugs as the
 437          * actual memory type might slightly differ from what Linux expects.
 438          */
 439         write_msr(MSR_IA32_PAT, PAT_RESET_VALUE);
 440
 441         /* We enter Linux at the point arch_entry would return to as well.
 442          * rax is cleared to signal success to the caller. */
 443         asm volatile(
 444                 "clgi\n\t"
 445                 "mov (%%rdi),%%r15\n\t"
 446                 "mov 0x8(%%rdi),%%r14\n\t"
 447                 "mov 0x10(%%rdi),%%r13\n\t"
 448                 "mov 0x18(%%rdi),%%r12\n\t"
 449                 "mov 0x20(%%rdi),%%rbx\n\t"
 450                 "mov 0x28(%%rdi),%%rbp\n\t"
 451                 "mov %0, %%rax\n\t"
 452                 "vmload %%rax\n\t"
 453                 "vmrun %%rax\n\t"
 454                 "vmsave %%rax\n\t"
 455                 /* Restore hypervisor stack */
 456                 "mov %2, %%rsp\n\t"
 457                 "jmp svm_vmexit"
 458                 : /* no output */
 459                 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
 460                 : "memory", "r15", "r14", "r13", "r12",
 461                   "rbx", "rbp", "rax", "cc");
 462         __builtin_unreachable();
 463 }
 464
 465 void __attribute__((noreturn))
 466 vcpu_deactivate_vmm(struct registers *guest_regs)
 467 {
 468         struct per_cpu *cpu_data = this_cpu_data();
 469         struct vmcb *vmcb = &cpu_data->vmcb;
 470         unsigned long *stack = (unsigned long *)vmcb->rsp;
 471         unsigned long linux_ip = vmcb->rip;
 472
 473         /* We are leaving - set the GIF */
 474         asm volatile ("stgi" : : : "memory");
 475
 476         /*
 477          * Restore the MSRs.
 478          *
 479          * XXX: One could argue this is better to be done in
 480          * arch_cpu_restore(), however, it would require changes
 481          * to cpu_data to store STAR and friends.
 482          */
 483         write_msr(MSR_STAR, vmcb->star);
 484         write_msr(MSR_LSTAR, vmcb->lstar);
 485         write_msr(MSR_CSTAR, vmcb->cstar);
 486         write_msr(MSR_SFMASK, vmcb->sfmask);
 487         write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
 488         write_msr(MSR_IA32_PAT, vmcb->g_pat);
 489
 490         cpu_data->linux_cr3 = vmcb->cr3;
 491
 492         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 493         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 494         cpu_data->linux_idtr.base = vmcb->idtr.base;
 495         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 496
 497         cpu_data->linux_cs.selector = vmcb->cs.selector;
 498
 499         cpu_data->linux_tss.selector = vmcb->tr.selector;
 500
 501         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 502         cpu_data->linux_fs.base = vmcb->fs.base;
 503         cpu_data->linux_gs.base = vmcb->gs.base;
 504
 505         cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
 506         cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
 507         cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
 508
 509         cpu_data->linux_ds.selector = vmcb->ds.selector;
 510         cpu_data->linux_es.selector = vmcb->es.selector;
 511         cpu_data->linux_fs.selector = vmcb->fs.selector;
 512         cpu_data->linux_gs.selector = vmcb->gs.selector;
 513
 514         arch_cpu_restore(cpu_data, 0);
 515
 516         stack--;
 517         *stack = linux_ip;
 518
 519         asm volatile (
 520                 "mov %%rbx,%%rsp\n\t"
 521                 "pop %%r15\n\t"
 522                 "pop %%r14\n\t"
 523                 "pop %%r13\n\t"
 524                 "pop %%r12\n\t"
 525                 "pop %%r11\n\t"
 526                 "pop %%r10\n\t"
 527                 "pop %%r9\n\t"
 528                 "pop %%r8\n\t"
 529                 "pop %%rdi\n\t"
 530                 "pop %%rsi\n\t"
 531                 "pop %%rbp\n\t"
 532                 "add $8,%%rsp\n\t"
 533                 "pop %%rbx\n\t"
 534                 "pop %%rdx\n\t"
 535                 "pop %%rcx\n\t"
 536                 "mov %%rax,%%rsp\n\t"
 537                 "xor %%rax,%%rax\n\t"
 538                 "ret"
 539                 : : "a" (stack), "b" (guest_regs));
 540         __builtin_unreachable();
 541 }
 542
 543 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 544 {
 545         struct vmcb *vmcb = &cpu_data->vmcb;
 546         unsigned long val;
 547         bool ok = true;
 548
 549         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 550         vmcb->cr3 = 0;
 551         vmcb->cr4 = 0;
 552
 553         vmcb->rflags = 0x02;
 554
 555         val = 0;
 556         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 557                 val = 0xfff0;
 558                 sipi_vector = 0xf0;
 559         }
 560         vmcb->rip = val;
 561         vmcb->rsp = 0;
 562
 563         vmcb->cs.selector = sipi_vector << 8;
 564         vmcb->cs.base = sipi_vector << 12;
 565         vmcb->cs.limit = 0xffff;
 566         vmcb->cs.access_rights = 0x009b;
 567
 568         vmcb->ds.selector = 0;
 569         vmcb->ds.base = 0;
 570         vmcb->ds.limit = 0xffff;
 571         vmcb->ds.access_rights = 0x0093;
 572
 573         vmcb->es.selector = 0;
 574         vmcb->es.base = 0;
 575         vmcb->es.limit = 0xffff;
 576         vmcb->es.access_rights = 0x0093;
 577
 578         vmcb->fs.selector = 0;
 579         vmcb->fs.base = 0;
 580         vmcb->fs.limit = 0xffff;
 581         vmcb->fs.access_rights = 0x0093;
 582
 583         vmcb->gs.selector = 0;
 584         vmcb->gs.base = 0;
 585         vmcb->gs.limit = 0xffff;
 586         vmcb->gs.access_rights = 0x0093;
 587
 588         vmcb->ss.selector = 0;
 589         vmcb->ss.base = 0;
 590         vmcb->ss.limit = 0xffff;
 591         vmcb->ss.access_rights = 0x0093;
 592
 593         vmcb->tr.selector = 0;
 594         vmcb->tr.base = 0;
 595         vmcb->tr.limit = 0xffff;
 596         vmcb->tr.access_rights = 0x008b;
 597
 598         vmcb->ldtr.selector = 0;
 599         vmcb->ldtr.base = 0;
 600         vmcb->ldtr.limit = 0xffff;
 601         vmcb->ldtr.access_rights = 0x0082;
 602
 603         vmcb->gdtr.selector = 0;
 604         vmcb->gdtr.base = 0;
 605         vmcb->gdtr.limit = 0xffff;
 606         vmcb->gdtr.access_rights = 0;
 607
 608         vmcb->idtr.selector = 0;
 609         vmcb->idtr.base = 0;
 610         vmcb->idtr.limit = 0xffff;
 611         vmcb->idtr.access_rights = 0;
 612
 613         vmcb->efer = EFER_SVME;
 614
 615         /* These MSRs are undefined on reset */
 616         vmcb->star = 0;
 617         vmcb->lstar = 0;
 618         vmcb->cstar = 0;
 619         vmcb->sfmask = 0;
 620         vmcb->sysenter_cs = 0;
 621         vmcb->sysenter_eip = 0;
 622         vmcb->sysenter_esp = 0;
 623         vmcb->kerngsbase = 0;
 624
 625         vmcb->g_pat = PAT_RESET_VALUE;
 626
 627         vmcb->dr7 = 0x00000400;
 628
 629         /* Almost all of the guest state changed */
 630         vmcb->clean_bits = 0;
 631
 632         ok &= svm_set_cell_config(cpu_data->cell, vmcb);
 633
 634         /* This is always false, but to be consistent with vmx.c... */
 635         if (!ok) {
 636                 panic_printk("FATAL: CPU reset failed\n");
 637                 panic_stop();
 638         }
 639 }
 640
 641 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 642 {
 643         struct per_cpu *cpu_data = this_cpu_data();
 644         struct vmcb *vmcb = &cpu_data->vmcb;
 645         vmcb->rip += inst_len;
 646 }
 647
 648 static void update_efer(struct per_cpu *cpu_data)
 649 {
 650         struct vmcb *vmcb = &cpu_data->vmcb;
 651         unsigned long efer = vmcb->efer;
 652
 653         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 654                 return;
 655
 656         efer |= EFER_LMA;
 657
 658         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 659         if ((vmcb->efer ^ efer) & EFER_LMA)
 660                 vcpu_tlb_flush();
 661
 662         vmcb->efer = efer;
 663         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 664 }
 665
 666 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 667 {
 668         struct per_cpu *cpu_data = this_cpu_data();
 669         struct vmcb *vmcb = &cpu_data->vmcb;
 670
 671         if (vmcb->efer & EFER_LMA) {
 672                 pg_structs->root_paging = x86_64_paging;
 673                 pg_structs->root_table_gphys =
 674                         vmcb->cr3 & 0x000ffffffffff000UL;
 675         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 676                    !(vmcb->cr4 & X86_CR4_PAE)) {
 677                 pg_structs->root_paging = i386_paging;
 678                 pg_structs->root_table_gphys =
 679                         vmcb->cr3 & 0xfffff000UL;
 680         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 681                 /*
 682                  * Can be in non-paged protected mode as well, but
 683                  * the translation mechanism will stay the same ayway.
 684                  */
 685                 pg_structs->root_paging = realmode_paging;
 686                 /*
 687                  * This will make paging_get_guest_pages map the page
 688                  * that also contains the bootstrap code and, thus, is
 689                  * always present in a cell.
 690                  */
 691                 pg_structs->root_table_gphys = 0xff000;
 692         } else {
 693                 printk("FATAL: Unsupported paging mode\n");
 694                 return false;
 695         }
 696         return true;
 697 }
 698
 699 struct parse_context {
 700         unsigned int remaining;
 701         unsigned int size;
 702         unsigned long cs_base;
 703         const u8 *inst;
 704 };
 705
 706 static bool ctx_advance(struct parse_context *ctx,
 707                         unsigned long *pc,
 708                         struct guest_paging_structures *pg_structs)
 709 {
 710         if (!ctx->size) {
 711                 ctx->size = ctx->remaining;
 712                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 713                                           &ctx->size);
 714                 if (!ctx->inst)
 715                         return false;
 716                 ctx->remaining -= ctx->size;
 717                 *pc += ctx->size;
 718         }
 719         return true;
 720 }
 721
 722 static bool x86_parse_mov_to_cr(struct per_cpu *cpu_data,
 723                                 unsigned long pc,
 724                                 unsigned char reg,
 725                                 unsigned long *gpr)
 726 {
 727         struct guest_paging_structures pg_structs;
 728         struct vmcb *vmcb = &cpu_data->vmcb;
 729         struct parse_context ctx = {};
 730         /* No prefixes are supported yet */
 731         u8 opcodes[] = {0x0f, 0x22}, modrm;
 732         bool ok = false;
 733         int n;
 734
 735         ctx.remaining = ARRAY_SIZE(opcodes);
 736         if (!vcpu_get_guest_paging_structs(&pg_structs))
 737                 goto out;
 738         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 739
 740         if (!ctx_advance(&ctx, &pc, &pg_structs))
 741                 goto out;
 742
 743         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
 744                 if (*(ctx.inst) != opcodes[n])
 745                         goto out;
 746                 if (!ctx_advance(&ctx, &pc, &pg_structs))
 747                         goto out;
 748         }
 749
 750         if (!ctx_advance(&ctx, &pc, &pg_structs))
 751                 goto out;
 752
 753         modrm = *(ctx.inst);
 754
 755         if (((modrm & 0x38) >> 3) != reg)
 756                 goto out;
 757
 758         if (gpr)
 759                 *gpr = (modrm & 0x7);
 760
 761         ok = true;
 762 out:
 763         return ok;
 764 }
 765
 766 /*
 767  * XXX: The only visible reason to have this function (vmx.c consistency
 768  * aside) is to prevent cells from setting invalid CD+NW combinations that
 769  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 770  * altogether?
 771  */
 772 static bool svm_handle_cr(struct registers *guest_regs,
 773                           struct per_cpu *cpu_data)
 774 {
 775         struct vmcb *vmcb = &cpu_data->vmcb;
 776         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 777         unsigned long reg = -1, val, bits;
 778         bool ok = true;
 779
 780         if (has_assists) {
 781                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 782                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 783                         ok = false;
 784                         goto out;
 785                 }
 786                 reg = vmcb->exitinfo1 & 0x07;
 787         } else {
 788                 if (!x86_parse_mov_to_cr(cpu_data, vmcb->rip, 0, &reg)) {
 789                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 790                         ok = false;
 791                         goto out;
 792                 }
 793         };
 794
 795         if (reg == 4)
 796                 val = vmcb->rsp;
 797         else
 798                 val = ((unsigned long *)guest_regs)[15 - reg];
 799
 800         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 801         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 802         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 803         if ((val ^ vmcb->cr0) & bits)
 804                 vcpu_tlb_flush();
 805         /* TODO: better check for #GP reasons */
 806         vmcb->cr0 = val & SVM_CR0_CLEARED_BITS;
 807         if (val & X86_CR0_PG)
 808                 update_efer(cpu_data);
 809         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 810
 811 out:
 812         return ok;
 813 }
 814
 815 static bool svm_handle_msr_read(struct registers *guest_regs,
 816                 struct per_cpu *cpu_data)
 817 {
 818         if (guest_regs->rcx >= MSR_X2APIC_BASE &&
 819             guest_regs->rcx <= MSR_X2APIC_END) {
 820                 vcpu_skip_emulated_instruction(X86_INST_LEN_RDMSR);
 821                 x2apic_handle_read(guest_regs);
 822                 return true;
 823         } else {
 824                 panic_printk("FATAL: Unhandled MSR read: %x\n",
 825                              guest_regs->rcx);
 826                 return false;
 827         }
 828 }
 829
 830 static bool svm_handle_msr_write(struct registers *guest_regs,
 831                 struct per_cpu *cpu_data)
 832 {
 833         struct vmcb *vmcb = &cpu_data->vmcb;
 834         unsigned long efer, val;
 835         bool result = true;
 836
 837         if (guest_regs->rcx >= MSR_X2APIC_BASE &&
 838             guest_regs->rcx <= MSR_X2APIC_END) {
 839                 result = x2apic_handle_write(guest_regs, cpu_data);
 840                 goto out;
 841         }
 842         if (guest_regs->rcx == MSR_EFER) {
 843                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 844                 efer = (guest_regs->rax & 0xffffffff) |
 845                         (guest_regs->rdx << 32) | EFER_SVME;
 846                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 847                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 848                         vcpu_tlb_flush();
 849                 vmcb->efer = efer;
 850                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 851                 goto out;
 852         }
 853         if (guest_regs->rcx == MTRR_DEFTYPE) {
 854                 val = (guest_regs->rax & 0xffffffff) | (guest_regs->rdx << 32);
 855                 /*
 856                  * Quick (and very incomplete) guest MTRRs emulation.
 857                  *
 858                  * For Linux, emulating MTRR Enable bit seems to be enough.
 859                  * If it is cleared, we set hPAT to all zeroes, effectively
 860                  * making all NPT-mapped memory UC (see APMv2, Sect. 15.25.8).
 861                  *
 862                  * Otherwise, default PAT value is restored. This can also
 863                  * make NPT-mapped memory's type different from what Linux
 864                  * expects, however.
 865                  */
 866                 if (val & 0x800)
 867                         write_msr(MSR_IA32_PAT, PAT_RESET_VALUE);
 868                 else
 869                         write_msr(MSR_IA32_PAT, 0);
 870                 goto out;
 871         }
 872
 873         result = false;
 874         panic_printk("FATAL: Unhandled MSR write: %x\n",
 875                      guest_regs->rcx);
 876 out:
 877         if (result)
 878                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 879         return result;
 880 }
 881
 882 /*
 883  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 884  * be treated separately in svm_handle_avic_access().
 885  */
 886 static bool svm_handle_apic_access(struct registers *guest_regs,
 887                                    struct per_cpu *cpu_data)
 888 {
 889         struct vmcb *vmcb = &cpu_data->vmcb;
 890         struct guest_paging_structures pg_structs;
 891         unsigned int inst_len, offset;
 892         bool is_write;
 893
 894         /* The caller is responsible for sanity checks */
 895         is_write = !!(vmcb->exitinfo1 & 0x2);
 896         offset = vmcb->exitinfo2 - XAPIC_BASE;
 897
 898         if (offset & 0x00f)
 899                 goto out_err;
 900
 901         if (!vcpu_get_guest_paging_structs(&pg_structs))
 902                 goto out_err;
 903
 904         inst_len = apic_mmio_access(guest_regs, cpu_data, vmcb->rip,
 905                                     &pg_structs, offset >> 4, is_write);
 906         if (!inst_len)
 907                 goto out_err;
 908
 909         vcpu_skip_emulated_instruction(inst_len);
 910         return true;
 911
 912 out_err:
 913         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 914                      offset, is_write);
 915         return false;
 916 }
 917
 918 static void dump_guest_regs(struct registers *guest_regs, struct vmcb *vmcb)
 919 {
 920         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 921                      vmcb->rsp, vmcb->rflags);
 922         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 923                      guest_regs->rbx, guest_regs->rcx);
 924         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 925                      guest_regs->rsi, guest_regs->rdi);
 926         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 927                      vmcb->cs.selector,
 928                      vmcb->cs.base,
 929                      vmcb->cs.access_rights,
 930                      (vmcb->efer & EFER_LMA));
 931         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 932                      vmcb->cr3, vmcb->cr4);
 933         panic_printk("EFER: %p\n", vmcb->efer);
 934 }
 935
 936 static void svm_get_vcpu_pf_intercept(struct per_cpu *cpu_data,
 937                                       struct vcpu_pf_intercept *out)
 938 {
 939         struct vmcb *vmcb = &cpu_data->vmcb;
 940
 941         out->phys_addr = vmcb->exitinfo2;
 942         out->is_write = !!(vmcb->exitinfo1 & 0x2);
 943 }
 944
 945 static void svm_get_vcpu_io_intercept(struct per_cpu *cpu_data,
 946                                       struct vcpu_io_intercept *out)
 947 {
 948         struct vmcb *vmcb = &cpu_data->vmcb;
 949         u64 exitinfo = vmcb->exitinfo1;
 950
 951         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 952         out->port = (exitinfo >> 16) & 0xFFFF;
 953         out->size = (exitinfo >> 4) & 0x7;
 954         out->in = !!(exitinfo & 0x1);
 955         out->inst_len = vmcb->exitinfo2 - vmcb->rip;
 956         out->rep_or_str = !!(exitinfo & 0x0c);
 957 }
 958
 959 void vcpu_handle_exit(struct registers *guest_regs, struct per_cpu *cpu_data)
 960 {
 961         struct vmcb *vmcb = &cpu_data->vmcb;
 962         struct vcpu_execution_state x_state;
 963         struct vcpu_pf_intercept pf;
 964         struct vcpu_io_intercept io;
 965         bool res = false;
 966         int sipi_vector;
 967
 968         /* Restore GS value expected by per_cpu data accessors */
 969         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 970
 971         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 972         /*
 973          * All guest state is marked unmodified; individual handlers must clear
 974          * the bits as needed.
 975          */
 976         vmcb->clean_bits = 0xffffffff;
 977
 978         switch (vmcb->exitcode) {
 979         case VMEXIT_INVALID:
 980                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 981                              vmcb->exitcode);
 982                 break;
 983         case VMEXIT_NMI:
 984                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 985                 /* Temporarily enable GIF to consume pending NMI */
 986                 asm volatile("stgi; clgi" : : : "memory");
 987                 sipi_vector = x86_handle_events(cpu_data);
 988                 if (sipi_vector >= 0) {
 989                         printk("CPU %d received SIPI, vector %x\n",
 990                                cpu_data->cpu_id, sipi_vector);
 991                         svm_vcpu_reset(cpu_data, sipi_vector);
 992                         memset(guest_regs, 0, sizeof(*guest_regs));
 993                 }
 994                 iommu_check_pending_faults(cpu_data);
 995                 return;
 996         case VMEXIT_CPUID:
 997                 /* FIXME: We are not intercepting CPUID now */
 998                 return;
 999         case VMEXIT_VMMCALL:
1000                 vcpu_vendor_get_execution_state(&x_state);
1001                 vcpu_handle_hypercall(guest_regs, &x_state);
1002                 return;
1003         case VMEXIT_CR0_SEL_WRITE:
1004                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
1005                 if (svm_handle_cr(guest_regs, cpu_data))
1006                         return;
1007                 break;
1008         case VMEXIT_MSR:
1009                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
1010                 if (!vmcb->exitinfo1)
1011                         res = svm_handle_msr_read(guest_regs, cpu_data);
1012                 else
1013                         res = svm_handle_msr_write(guest_regs, cpu_data);
1014                 if (res)
1015                         return;
1016                 break;
1017         case VMEXIT_NPF:
1018                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
1019                      vmcb->exitinfo2 >= XAPIC_BASE &&
1020                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
1021                         /* APIC access in non-AVIC mode */
1022                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
1023                         if (svm_handle_apic_access(guest_regs, cpu_data))
1024                                 return;
1025                 } else {
1026                         /* General MMIO (IOAPIC, PCI etc) */
1027                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
1028                         svm_get_vcpu_pf_intercept(cpu_data, &pf);
1029                         if (vcpu_handle_pt_violation(guest_regs, &pf))
1030                                 return;
1031                 }
1032
1033                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
1034                              "error code is %x\n", vmcb->exitinfo2,
1035                              vmcb->exitinfo1 & 0xf);
1036                 break;
1037         case VMEXIT_XSETBV:
1038                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XSETBV]++;
1039                 if ((guest_regs->rax & X86_XCR0_FP) &&
1040                     (guest_regs->rax & ~cpuid_eax(0x0d)) == 0 &&
1041                     guest_regs->rcx == 0 && guest_regs->rdx == 0) {
1042                         vcpu_skip_emulated_instruction(X86_INST_LEN_XSETBV);
1043                         asm volatile(
1044                                 "xsetbv"
1045                                 : /* no output */
1046                                 : "a" (guest_regs->rax), "c" (0), "d" (0));
1047                         return;
1048                 }
1049                 panic_printk("FATAL: Invalid xsetbv parameters: "
1050                              "xcr[%d] = %x:%x\n", guest_regs->rcx,
1051                              guest_regs->rdx, guest_regs->rax);
1052                 break;
1053         case VMEXIT_IOIO:
1054                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
1055                 svm_get_vcpu_io_intercept(cpu_data, &io);
1056                 if (vcpu_handle_io_access(guest_regs, &io))
1057                         return;
1058                 break;
1059         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
1060         default:
1061                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
1062                              "exitinfo1 %p exitinfo2 %p\n",
1063                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
1064         }
1065         dump_guest_regs(guest_regs, vmcb);
1066         panic_park();
1067 }
1068
1069 void vcpu_park(struct per_cpu *cpu_data)
1070 {
1071         struct vmcb *vmcb = &cpu_data->vmcb;
1072
1073         svm_vcpu_reset(cpu_data, APIC_BSP_PSEUDO_SIPI);
1074         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
1075         vmcb->n_cr3 = paging_hvirt2phys(parked_mode_npt);
1076
1077         vcpu_tlb_flush();
1078 }
1079
1080 void vcpu_nmi_handler(void)
1081 {
1082 }
1083
1084 void vcpu_tlb_flush(void)
1085 {
1086         struct per_cpu *cpu_data = this_cpu_data();
1087         struct vmcb *vmcb = &cpu_data->vmcb;
1088
1089         if (has_flush_by_asid)
1090                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1091         else
1092                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1093 }
1094
1095 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1096                               unsigned long pc, unsigned int *size)
1097 {
1098         struct per_cpu *cpu_data = this_cpu_data();
1099         struct vmcb *vmcb = &cpu_data->vmcb;
1100         unsigned long start;
1101
1102         if (has_assists) {
1103                 if (!*size)
1104                         return NULL;
1105                 start = vmcb->rip - pc;
1106                 if (start < vmcb->bytes_fetched) {
1107                         *size = vmcb->bytes_fetched - start;
1108                         return &vmcb->guest_bytes[start];
1109                 } else {
1110                         return NULL;
1111                 }
1112         } else {
1113                 return vcpu_map_inst(pg_structs, pc, size);
1114         }
1115 }
1116
1117 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1118                                     struct vcpu_io_bitmap *iobm)
1119 {
1120         iobm->data = cell->svm.iopm;
1121         iobm->size = sizeof(cell->svm.iopm);
1122 }
1123
1124 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1125 {
1126         struct per_cpu *cpu_data = this_cpu_data();
1127
1128         x_state->efer = cpu_data->vmcb.efer;
1129         x_state->rflags = cpu_data->vmcb.rflags;
1130         x_state->cs = cpu_data->vmcb.cs.selector;
1131         x_state->rip = cpu_data->vmcb.rip;
1132 }
1133
1134 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1135 void enable_irq(void)
1136 {
1137         asm volatile("stgi; sti" : : : "memory");
1138 }
1139
1140 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1141 void disable_irq(void)
1142 {
1143         asm volatile("cli; clgi" : : : "memory");
1144 }