hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell.h>
  19 #include <jailhouse/cell-config.h>
  20 #include <jailhouse/control.h>
  21 #include <jailhouse/paging.h>
  22 #include <jailhouse/printk.h>
  23 #include <jailhouse/processor.h>
  24 #include <jailhouse/string.h>
  25 #include <jailhouse/utils.h>
  26 #include <asm/apic.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 /* IOPM size: two 4-K pages + 3 bits */
  43 #define IOPM_PAGES              3
  44
  45 static bool has_avic, has_assists, has_flush_by_asid;
  46
  47 static const struct segment invalid_seg;
  48
  49 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  50
  51 /* bit cleared: direct access allowed */
  52 // TODO: convert to whitelist
  53 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  54         [ SVM_MSRPM_0000 ] = {
  55                 [      0/4 ...  0x017/4 ] = 0,
  56                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  57                 [  0x01c/4 ...  0x1ff/4 ] = 0,
  58                 [  0x200/4 ...  0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
  59                 [  0x274/4 ...  0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
  60                 [  0x278/4 ...  0x2fb/4 ] = 0,
  61                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  62                 [  0x300/4 ...  0x7ff/4 ] = 0,
  63                 /* x2APIC MSRs - emulated if not present */
  64                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  65                 [  0x804/4 ...  0x807/4 ] = 0,
  66                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  67                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  68                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  69                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  70                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  71                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  72                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  73                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  74                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  75                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  76                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  77                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  78                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  79                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  80                 [  0x840/4 ... 0x1fff/4 ] = 0,
  81         },
  82         [ SVM_MSRPM_C000 ] = {
  83                 [      0/4 ...  0x07f/4 ] = 0,
  84                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  85                 [  0x084/4 ... 0x1fff/4 ] = 0
  86         },
  87         [ SVM_MSRPM_C001 ] = {
  88                 [      0/4 ... 0x1fff/4 ] = 0,
  89         },
  90         [ SVM_MSRPM_RESV ] = {
  91                 [      0/4 ... 0x1fff/4 ] = 0,
  92         }
  93 };
  94
  95 /* This page is mapped so the code begins at 0x000ffff0 */
  96 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  97         [0xff0] = 0xfa, /* 1: cli */
  98         [0xff1] = 0xf4, /*    hlt */
  99         [0xff2] = 0xeb,
 100         [0xff3] = 0xfc  /*    jmp 1b */
 101 };
 102
 103 static void *parked_mode_npt;
 104
 105 static void *avic_page;
 106
 107 static int svm_check_features(void)
 108 {
 109         /* SVM is available */
 110         if (!(cpuid_ecx(0x80000001, 0) & X86_FEATURE_SVM))
 111                 return trace_error(-ENODEV);
 112
 113         /* Nested paging */
 114         if (!(cpuid_edx(0x8000000A, 0) & X86_FEATURE_NP))
 115                 return trace_error(-EIO);
 116
 117         /* Decode assists */
 118         if ((cpuid_edx(0x8000000A, 0) & X86_FEATURE_DECODE_ASSISTS))
 119                 has_assists = true;
 120
 121         /* AVIC support */
 122         /* FIXME: Jailhouse support is incomplete so far
 123         if (cpuid_edx(0x8000000A, 0) & X86_FEATURE_AVIC)
 124                 has_avic = true; */
 125
 126         /* TLB Flush by ASID support */
 127         if (cpuid_edx(0x8000000A, 0) & X86_FEATURE_FLUSH_BY_ASID)
 128                 has_flush_by_asid = true;
 129
 130         return 0;
 131 }
 132
 133 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 134                                      const struct desc_table_reg *dtr)
 135 {
 136         svm_segment->base = dtr->base;
 137         svm_segment->limit = dtr->limit & 0xffff;
 138 }
 139
 140 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 141                                          const struct segment *segment)
 142 {
 143         svm_segment->selector = segment->selector;
 144         svm_segment->access_rights = ((segment->access_rights & 0xf000) >> 4) |
 145                 (segment->access_rights & 0x00ff);
 146         svm_segment->limit = segment->limit;
 147         svm_segment->base = segment->base;
 148 }
 149
 150 static void svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 151 {
 152         vmcb->iopm_base_pa = paging_hvirt2phys(cell->arch.svm.iopm);
 153         vmcb->n_cr3 = paging_hvirt2phys(cell->arch.svm.npt_structs.root_table);
 154 }
 155
 156 static void vmcb_setup(struct per_cpu *cpu_data)
 157 {
 158         struct vmcb *vmcb = &cpu_data->vmcb;
 159
 160         memset(vmcb, 0, sizeof(struct vmcb));
 161
 162         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 163         vmcb->cr3 = cpu_data->linux_cr3;
 164         vmcb->cr4 = cpu_data->linux_cr4;
 165
 166         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 167         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 168         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 169         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 170         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 171         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 172         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 173         set_svm_segment_from_segment(&vmcb->ldtr, &invalid_seg);
 174
 175         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 176         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 177
 178         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 179
 180         vmcb->rflags = 0x02;
 181         /* Indicate success to the caller of arch_entry */
 182         vmcb->rax = 0;
 183         vmcb->rsp = cpu_data->linux_sp +
 184                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 185         vmcb->rip = cpu_data->linux_ip;
 186
 187         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 188         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 189         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 190         vmcb->star = read_msr(MSR_STAR);
 191         vmcb->lstar = read_msr(MSR_LSTAR);
 192         vmcb->cstar = read_msr(MSR_CSTAR);
 193         vmcb->sfmask = read_msr(MSR_SFMASK);
 194         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 195
 196         vmcb->dr6 = 0x00000ff0;
 197         vmcb->dr7 = 0x00000400;
 198
 199         /* Make the hypervisor visible */
 200         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 201
 202         vmcb->g_pat = cpu_data->pat;
 203
 204         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 205         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 206         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID;
 207         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 208         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 209         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 210
 211         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 212         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 213
 214         /*
 215          * We only intercept #DB and #AC to prevent that malicious guests can
 216          * trigger infinite loops in microcode (see e.g. CVE-2015-5307 and
 217          * CVE-2015-8104).
 218          */
 219         vmcb->exception_intercepts |= (1 << DB_VECTOR) | (1 << AC_VECTOR);
 220
 221         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 222
 223         vmcb->np_enable = 1;
 224         /* No more than one guest owns the CPU */
 225         vmcb->guest_asid = 1;
 226
 227         /* TODO: Setup AVIC */
 228
 229         /* Explicitly mark all of the state as new */
 230         vmcb->clean_bits = 0;
 231
 232         svm_set_cell_config(cpu_data->cell, vmcb);
 233 }
 234
 235 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 236                                      unsigned long gphys,
 237                                      unsigned long flags)
 238 {
 239         return paging_virt2phys(&cpu_data->cell->arch.svm.npt_structs,
 240                         gphys, flags);
 241 }
 242
 243 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 244 {
 245         /* See APMv2, Section 15.25.5 */
 246         *pte = (next_pt & BIT_MASK(51, 12)) | PAGE_DEFAULT_FLAGS | PAGE_FLAG_US;
 247 }
 248
 249 int vcpu_vendor_init(void)
 250 {
 251         struct paging_structures parking_pt;
 252         unsigned long vm_cr;
 253         int err, n;
 254
 255         err = svm_check_features();
 256         if (err)
 257                 return err;
 258
 259         vm_cr = read_msr(MSR_VM_CR);
 260         if (vm_cr & VM_CR_SVMDIS)
 261                 /* SVM disabled in BIOS */
 262                 return trace_error(-EPERM);
 263
 264         /* Nested paging is the same as the native one */
 265         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 266         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 267                 npt_paging[n].set_next_pt = npt_set_next_pt;
 268
 269         /* Map guest parking code (shared between cells and CPUs) */
 270         parking_pt.root_paging = npt_paging;
 271         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 272         if (!parked_mode_npt)
 273                 return -ENOMEM;
 274         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 275                             PAGE_SIZE, 0x000ff000,
 276                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 277                             PAGING_NON_COHERENT);
 278         if (err)
 279                 return err;
 280
 281         /* This is always false for AMD now (except in nested SVM);
 282            see Sect. 16.3.1 in APMv2 */
 283         if (using_x2apic) {
 284                 /* allow direct x2APIC access except for ICR writes */
 285                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 286                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 287                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 288         } else {
 289                 if (has_avic) {
 290                         avic_page = page_alloc(&remap_pool, 1);
 291                         if (!avic_page)
 292                                 return trace_error(-ENOMEM);
 293                 }
 294         }
 295
 296         return vcpu_cell_init(&root_cell);
 297 }
 298
 299 int vcpu_vendor_cell_init(struct cell *cell)
 300 {
 301         int err = -ENOMEM;
 302         u64 flags;
 303
 304         /* allocate iopm  */
 305         cell->arch.svm.iopm = page_alloc(&mem_pool, IOPM_PAGES);
 306         if (!cell->arch.svm.iopm)
 307                 return err;
 308
 309         /* build root NPT of cell */
 310         cell->arch.svm.npt_structs.root_paging = npt_paging;
 311         cell->arch.svm.npt_structs.root_table =
 312                 (page_table_t)cell->arch.root_table_page;
 313
 314         if (!has_avic) {
 315                 /*
 316                  * Map xAPIC as is; reads are passed, writes are trapped.
 317                  */
 318                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 319                 err = paging_create(&cell->arch.svm.npt_structs, XAPIC_BASE,
 320                                     PAGE_SIZE, XAPIC_BASE,
 321                                     flags,
 322                                     PAGING_NON_COHERENT);
 323         } else {
 324                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 325                 err = paging_create(&cell->arch.svm.npt_structs,
 326                                     paging_hvirt2phys(avic_page),
 327                                     PAGE_SIZE, XAPIC_BASE,
 328                                     flags,
 329                                     PAGING_NON_COHERENT);
 330         }
 331         if (err)
 332                 goto err_free_iopm;
 333
 334         return 0;
 335
 336 err_free_iopm:
 337         page_free(&mem_pool, cell->arch.svm.iopm, 3);
 338
 339         return err;
 340 }
 341
 342 int vcpu_map_memory_region(struct cell *cell,
 343                            const struct jailhouse_memory *mem)
 344 {
 345         u64 phys_start = mem->phys_start;
 346         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 347
 348         if (mem->flags & JAILHOUSE_MEM_READ)
 349                 flags |= PAGE_FLAG_PRESENT;
 350         if (mem->flags & JAILHOUSE_MEM_WRITE)
 351                 flags |= PAGE_FLAG_RW;
 352         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 353                 flags |= PAGE_FLAG_NOEXECUTE;
 354         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 355                 phys_start = paging_hvirt2phys(&cell->comm_page);
 356
 357         return paging_create(&cell->arch.svm.npt_structs, phys_start, mem->size,
 358                              mem->virt_start, flags, PAGING_NON_COHERENT);
 359 }
 360
 361 int vcpu_unmap_memory_region(struct cell *cell,
 362                              const struct jailhouse_memory *mem)
 363 {
 364         return paging_destroy(&cell->arch.svm.npt_structs, mem->virt_start,
 365                               mem->size, PAGING_NON_COHERENT);
 366 }
 367
 368 void vcpu_vendor_cell_exit(struct cell *cell)
 369 {
 370         paging_destroy(&cell->arch.svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 371                        PAGING_NON_COHERENT);
 372         page_free(&mem_pool, cell->arch.svm.iopm, 3);
 373 }
 374
 375 int vcpu_init(struct per_cpu *cpu_data)
 376 {
 377         unsigned long efer;
 378         int err;
 379
 380         err = svm_check_features();
 381         if (err)
 382                 return err;
 383
 384         efer = read_msr(MSR_EFER);
 385         if (efer & EFER_SVME)
 386                 return trace_error(-EBUSY);
 387
 388         efer |= EFER_SVME;
 389         write_msr(MSR_EFER, efer);
 390
 391         cpu_data->svm_state = SVMON;
 392
 393         vmcb_setup(cpu_data);
 394
 395         /*
 396          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 397          * set the values of reserved bits to the values found during the
 398          * previous CR0 read."
 399          * But we want to avoid surprises with new features unknown to us but
 400          * set by Linux. So check if any assumed revered bit was set and bail
 401          * out if so.
 402          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 403          */
 404         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 405                 return -EIO;
 406
 407         /* bring CR0 and CR4 into well-defined states */
 408         write_cr0(X86_CR0_HOST_STATE);
 409         write_cr4(X86_CR4_HOST_STATE);
 410
 411         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 412
 413         return 0;
 414 }
 415
 416 void vcpu_exit(struct per_cpu *cpu_data)
 417 {
 418         unsigned long efer;
 419
 420         if (cpu_data->svm_state == SVMOFF)
 421                 return;
 422
 423         cpu_data->svm_state = SVMOFF;
 424
 425         /* We are leaving - set the GIF */
 426         asm volatile ("stgi" : : : "memory");
 427
 428         efer = read_msr(MSR_EFER);
 429         efer &= ~EFER_SVME;
 430         write_msr(MSR_EFER, efer);
 431
 432         write_msr(MSR_VM_HSAVE_PA, 0);
 433 }
 434
 435 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 436 {
 437         unsigned long vmcb_pa, host_stack;
 438
 439         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 440         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 441
 442         /* We enter Linux at the point arch_entry would return to as well.
 443          * rax is cleared to signal success to the caller. */
 444         asm volatile(
 445                 "clgi\n\t"
 446                 "mov (%%rdi),%%r15\n\t"
 447                 "mov 0x8(%%rdi),%%r14\n\t"
 448                 "mov 0x10(%%rdi),%%r13\n\t"
 449                 "mov 0x18(%%rdi),%%r12\n\t"
 450                 "mov 0x20(%%rdi),%%rbx\n\t"
 451                 "mov 0x28(%%rdi),%%rbp\n\t"
 452                 "mov %2,%%rsp\n\t"
 453                 "vmload %%rax\n\t"
 454                 "jmp svm_vmentry"
 455                 : /* no output */
 456                 : "D" (cpu_data->linux_reg), "a" (vmcb_pa), "m" (host_stack));
 457         __builtin_unreachable();
 458 }
 459
 460 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
 461 {
 462         struct per_cpu *cpu_data = this_cpu_data();
 463         struct vmcb *vmcb = &cpu_data->vmcb;
 464         unsigned long *stack = (unsigned long *)vmcb->rsp;
 465         unsigned long linux_ip = vmcb->rip;
 466
 467         cpu_data->linux_cr0 = vmcb->cr0;
 468         cpu_data->linux_cr3 = vmcb->cr3;
 469
 470         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 471         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 472         cpu_data->linux_idtr.base = vmcb->idtr.base;
 473         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 474
 475         cpu_data->linux_cs.selector = vmcb->cs.selector;
 476
 477         asm volatile("str %0" : "=m" (cpu_data->linux_tss.selector));
 478
 479         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 480         cpu_data->linux_fs.base = read_msr(MSR_FS_BASE);
 481         cpu_data->linux_gs.base = vmcb->gs.base;
 482
 483         cpu_data->linux_ds.selector = vmcb->ds.selector;
 484         cpu_data->linux_es.selector = vmcb->es.selector;
 485
 486         asm volatile("mov %%fs,%0" : "=m" (cpu_data->linux_fs.selector));
 487         asm volatile("mov %%gs,%0" : "=m" (cpu_data->linux_gs.selector));
 488
 489         arch_cpu_restore(cpu_data, 0);
 490
 491         stack--;
 492         *stack = linux_ip;
 493
 494         asm volatile (
 495                 "mov %%rbx,%%rsp\n\t"
 496                 "pop %%r15\n\t"
 497                 "pop %%r14\n\t"
 498                 "pop %%r13\n\t"
 499                 "pop %%r12\n\t"
 500                 "pop %%r11\n\t"
 501                 "pop %%r10\n\t"
 502                 "pop %%r9\n\t"
 503                 "pop %%r8\n\t"
 504                 "pop %%rdi\n\t"
 505                 "pop %%rsi\n\t"
 506                 "pop %%rbp\n\t"
 507                 "add $8,%%rsp\n\t"
 508                 "pop %%rbx\n\t"
 509                 "pop %%rdx\n\t"
 510                 "pop %%rcx\n\t"
 511                 "mov %%rax,%%rsp\n\t"
 512                 "xor %%rax,%%rax\n\t"
 513                 "ret"
 514                 : : "a" (stack), "b" (&cpu_data->guest_regs));
 515         __builtin_unreachable();
 516 }
 517
 518 void vcpu_vendor_reset(unsigned int sipi_vector)
 519 {
 520         static const struct svm_segment dataseg_reset_state = {
 521                 .selector = 0,
 522                 .base = 0,
 523                 .limit = 0xffff,
 524                 .access_rights = 0x0093,
 525         };
 526         static const struct svm_segment dtr_reset_state = {
 527                 .selector = 0,
 528                 .base = 0,
 529                 .limit = 0xffff,
 530                 .access_rights = 0,
 531         };
 532         struct per_cpu *cpu_data = this_cpu_data();
 533         struct vmcb *vmcb = &cpu_data->vmcb;
 534         unsigned long val;
 535
 536         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 537         vmcb->cr3 = 0;
 538         vmcb->cr4 = 0;
 539
 540         vmcb->rflags = 0x02;
 541
 542         val = 0;
 543         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 544                 val = 0xfff0;
 545                 sipi_vector = 0xf0;
 546         }
 547         vmcb->rip = val;
 548         vmcb->rsp = 0;
 549
 550         vmcb->cs.selector = sipi_vector << 8;
 551         vmcb->cs.base = sipi_vector << 12;
 552         vmcb->cs.limit = 0xffff;
 553         vmcb->cs.access_rights = 0x009b;
 554
 555         vmcb->ds = dataseg_reset_state;
 556         vmcb->es = dataseg_reset_state;
 557         vmcb->fs = dataseg_reset_state;
 558         vmcb->gs = dataseg_reset_state;
 559         vmcb->ss = dataseg_reset_state;
 560
 561         vmcb->tr.selector = 0;
 562         vmcb->tr.base = 0;
 563         vmcb->tr.limit = 0xffff;
 564         vmcb->tr.access_rights = 0x008b;
 565
 566         vmcb->ldtr.selector = 0;
 567         vmcb->ldtr.base = 0;
 568         vmcb->ldtr.limit = 0xffff;
 569         vmcb->ldtr.access_rights = 0x0082;
 570
 571         vmcb->gdtr = dtr_reset_state;
 572         vmcb->idtr = dtr_reset_state;
 573
 574         vmcb->efer = EFER_SVME;
 575
 576         /* These MSRs are undefined on reset */
 577         vmcb->star = 0;
 578         vmcb->lstar = 0;
 579         vmcb->cstar = 0;
 580         vmcb->sfmask = 0;
 581         vmcb->sysenter_cs = 0;
 582         vmcb->sysenter_eip = 0;
 583         vmcb->sysenter_esp = 0;
 584         vmcb->kerngsbase = 0;
 585
 586         vmcb->dr7 = 0x00000400;
 587
 588         vmcb->eventinj = 0;
 589
 590         /* Almost all of the guest state changed */
 591         vmcb->clean_bits = 0;
 592
 593         svm_set_cell_config(cpu_data->cell, vmcb);
 594
 595         asm volatile(
 596                 "vmload %%rax"
 597                 : : "a" (paging_hvirt2phys(vmcb)) : "memory");
 598         /* vmload overwrites GS_BASE - restore the host state */
 599         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 600 }
 601
 602 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 603 {
 604         this_cpu_data()->vmcb.rip += inst_len;
 605 }
 606
 607 static void update_efer(struct vmcb *vmcb)
 608 {
 609         unsigned long efer = vmcb->efer;
 610
 611         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 612                 return;
 613
 614         efer |= EFER_LMA;
 615
 616         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 617         if ((vmcb->efer ^ efer) & EFER_LMA)
 618                 vcpu_tlb_flush();
 619
 620         vmcb->efer = efer;
 621         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 622 }
 623
 624 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 625 {
 626         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 627
 628         if (vmcb->efer & EFER_LMA) {
 629                 pg_structs->root_paging = x86_64_paging;
 630                 pg_structs->root_table_gphys = vmcb->cr3 & BIT_MASK(51, 12);
 631         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 632                    !(vmcb->cr4 & X86_CR4_PAE)) {
 633                 pg_structs->root_paging = i386_paging;
 634                 pg_structs->root_table_gphys = vmcb->cr3 & BIT_MASK(31, 12);
 635         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 636                 /*
 637                  * Can be in non-paged protected mode as well, but
 638                  * the translation mechanism will stay the same ayway.
 639                  */
 640                 pg_structs->root_paging = realmode_paging;
 641                 /*
 642                  * This will make paging_get_guest_pages map the page
 643                  * that also contains the bootstrap code and, thus, is
 644                  * always present in a cell.
 645                  */
 646                 pg_structs->root_table_gphys = 0xff000;
 647         } else {
 648                 printk("FATAL: Unsupported paging mode\n");
 649                 return false;
 650         }
 651         return true;
 652 }
 653
 654 void vcpu_vendor_set_guest_pat(unsigned long val)
 655 {
 656         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 657
 658         vmcb->g_pat = val;
 659         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 660 }
 661
 662 struct parse_context {
 663         unsigned int remaining;
 664         unsigned int size;
 665         unsigned long cs_base;
 666         const u8 *inst;
 667 };
 668
 669 static bool ctx_advance(struct parse_context *ctx,
 670                         unsigned long *pc,
 671                         struct guest_paging_structures *pg_structs)
 672 {
 673         if (!ctx->size) {
 674                 ctx->size = ctx->remaining;
 675                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 676                                           &ctx->size);
 677                 if (!ctx->inst)
 678                         return false;
 679                 ctx->remaining -= ctx->size;
 680                 *pc += ctx->size;
 681         }
 682         return true;
 683 }
 684
 685 static bool svm_parse_mov_to_cr(struct vmcb *vmcb, unsigned long pc,
 686                                 unsigned char reg, unsigned long *gpr)
 687 {
 688         struct guest_paging_structures pg_structs;
 689         struct parse_context ctx = {};
 690         /* No prefixes are supported yet */
 691         u8 opcodes[] = {0x0f, 0x22}, modrm;
 692         int n;
 693
 694         ctx.remaining = ARRAY_SIZE(opcodes);
 695         if (!vcpu_get_guest_paging_structs(&pg_structs))
 696                 return false;
 697         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 698
 699         if (!ctx_advance(&ctx, &pc, &pg_structs))
 700                 return false;
 701
 702         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++)
 703                 if (*(ctx.inst) != opcodes[n] ||
 704                     !ctx_advance(&ctx, &pc, &pg_structs))
 705                         return false;
 706
 707         if (!ctx_advance(&ctx, &pc, &pg_structs))
 708                 return false;
 709
 710         modrm = *(ctx.inst);
 711
 712         if (((modrm & 0x38) >> 3) != reg)
 713                 return false;
 714
 715         if (gpr)
 716                 *gpr = (modrm & 0x7);
 717
 718         return true;
 719 }
 720
 721 /*
 722  * XXX: The only visible reason to have this function (vmx.c consistency
 723  * aside) is to prevent cells from setting invalid CD+NW combinations that
 724  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 725  * altogether?
 726  */
 727 static bool svm_handle_cr(struct per_cpu *cpu_data)
 728 {
 729         struct vmcb *vmcb = &cpu_data->vmcb;
 730         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 731         unsigned long reg = -1, val, bits;
 732
 733         if (has_assists) {
 734                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 735                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 736                         return false;
 737                 }
 738                 reg = vmcb->exitinfo1 & 0x07;
 739         } else {
 740                 if (!svm_parse_mov_to_cr(vmcb, vmcb->rip, 0, &reg)) {
 741                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 742                         return false;
 743                 }
 744         }
 745
 746         if (reg == 4)
 747                 val = vmcb->rsp;
 748         else
 749                 val = cpu_data->guest_regs.by_index[15 - reg];
 750
 751         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 752         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 753         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 754         if ((val ^ vmcb->cr0) & bits)
 755                 vcpu_tlb_flush();
 756         /* TODO: better check for #GP reasons */
 757         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 758         if (val & X86_CR0_PG)
 759                 update_efer(vmcb);
 760         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 761
 762         return true;
 763 }
 764
 765 static bool svm_handle_msr_write(struct per_cpu *cpu_data)
 766 {
 767         struct vmcb *vmcb = &cpu_data->vmcb;
 768         unsigned long efer;
 769
 770         if (cpu_data->guest_regs.rcx == MSR_EFER) {
 771                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 772                 efer = get_wrmsr_value(&cpu_data->guest_regs) | EFER_SVME;
 773                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 774                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 775                         vcpu_tlb_flush();
 776                 vmcb->efer = efer;
 777                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 778                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 779                 return true;
 780         }
 781
 782         return vcpu_handle_msr_write();
 783 }
 784
 785 /*
 786  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 787  * be treated separately in svm_handle_avic_access().
 788  */
 789 static bool svm_handle_apic_access(struct vmcb *vmcb)
 790 {
 791         struct guest_paging_structures pg_structs;
 792         unsigned int inst_len, offset;
 793         bool is_write;
 794
 795         /* The caller is responsible for sanity checks */
 796         is_write = !!(vmcb->exitinfo1 & 0x2);
 797         offset = vmcb->exitinfo2 - XAPIC_BASE;
 798
 799         if (offset & 0x00f)
 800                 goto out_err;
 801
 802         if (!vcpu_get_guest_paging_structs(&pg_structs))
 803                 goto out_err;
 804
 805         inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
 806                                     is_write);
 807         if (!inst_len)
 808                 goto out_err;
 809
 810         vcpu_skip_emulated_instruction(inst_len);
 811         return true;
 812
 813 out_err:
 814         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 815                      offset, is_write);
 816         return false;
 817 }
 818
 819 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
 820 {
 821         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 822                      vmcb->rsp, vmcb->rflags);
 823         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 824                      guest_regs->rbx, guest_regs->rcx);
 825         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 826                      guest_regs->rsi, guest_regs->rdi);
 827         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 828                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 829                      !!(vmcb->efer & EFER_LMA));
 830         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 831                      vmcb->cr3, vmcb->cr4);
 832         panic_printk("EFER: %p\n", vmcb->efer);
 833 }
 834
 835 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
 836 {
 837         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 838         u64 exitinfo = vmcb->exitinfo1;
 839
 840         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 841         io->port = (exitinfo >> 16) & 0xFFFF;
 842         io->size = (exitinfo >> 4) & 0x7;
 843         io->in = !!(exitinfo & 0x1);
 844         io->inst_len = vmcb->exitinfo2 - vmcb->rip;
 845         io->rep_or_str = !!(exitinfo & 0x0c);
 846 }
 847
 848 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
 849 {
 850         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 851
 852         mmio->phys_addr = vmcb->exitinfo2;
 853         mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
 854 }
 855
 856 void vcpu_handle_exit(struct per_cpu *cpu_data)
 857 {
 858         struct vmcb *vmcb = &cpu_data->vmcb;
 859         bool res = false;
 860
 861         vmcb->gs.base = read_msr(MSR_GS_BASE);
 862
 863         /* Restore GS value expected by per_cpu data accessors */
 864         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 865
 866         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 867         /*
 868          * All guest state is marked unmodified; individual handlers must clear
 869          * the bits as needed.
 870          */
 871         vmcb->clean_bits = 0xffffffff;
 872
 873         switch (vmcb->exitcode) {
 874         case VMEXIT_INVALID:
 875                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 876                              vmcb->exitcode);
 877                 break;
 878         case VMEXIT_NMI:
 879                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 880                 /* Temporarily enable GIF to consume pending NMI */
 881                 asm volatile("stgi; clgi" : : : "memory");
 882                 x86_check_events();
 883                 goto vmentry;
 884         case VMEXIT_VMMCALL:
 885                 vcpu_handle_hypercall();
 886                 goto vmentry;
 887         case VMEXIT_CR0_SEL_WRITE:
 888                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 889                 if (svm_handle_cr(cpu_data))
 890                         goto vmentry;
 891                 break;
 892         case VMEXIT_CPUID:
 893                 vcpu_handle_cpuid();
 894                 goto vmentry;
 895         case VMEXIT_MSR:
 896                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 897                 if (!vmcb->exitinfo1)
 898                         res = vcpu_handle_msr_read();
 899                 else
 900                         res = svm_handle_msr_write(cpu_data);
 901                 if (res)
 902                         goto vmentry;
 903                 break;
 904         case VMEXIT_NPF:
 905                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
 906                      vmcb->exitinfo2 >= XAPIC_BASE &&
 907                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
 908                         /* APIC access in non-AVIC mode */
 909                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
 910                         if (svm_handle_apic_access(vmcb))
 911                                 goto vmentry;
 912                 } else {
 913                         /* General MMIO (IOAPIC, PCI etc) */
 914                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
 915                         if (vcpu_handle_mmio_access())
 916                                 goto vmentry;
 917                 }
 918                 break;
 919         case VMEXIT_XSETBV:
 920                 if (vcpu_handle_xsetbv())
 921                         goto vmentry;
 922                 break;
 923         case VMEXIT_IOIO:
 924                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
 925                 if (vcpu_handle_io_access())
 926                         goto vmentry;
 927                 break;
 928         case VMEXIT_EXCEPTION_DB:
 929         case VMEXIT_EXCEPTION_AC:
 930                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_EXCEPTION]++;
 931                 /* Reinject exception, including error code if needed. */
 932                 vmcb->eventinj = (vmcb->exitcode - VMEXIT_EXCEPTION_DE) |
 933                         SVM_EVENTINJ_EXCEPTION | SVM_EVENTINJ_VALID;
 934                 if (vmcb->exitcode == VMEXIT_EXCEPTION_AC) {
 935                         vmcb->eventinj |= SVM_EVENTINJ_ERR_VALID;
 936                         vmcb->eventinj_err = vmcb->exitinfo1;
 937                 }
 938                 x86_check_events();
 939                 goto vmentry;
 940         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
 941         default:
 942                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
 943                              "exitinfo1 %p exitinfo2 %p\n",
 944                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
 945         }
 946         dump_guest_regs(&cpu_data->guest_regs, vmcb);
 947         panic_park();
 948
 949 vmentry:
 950         write_msr(MSR_GS_BASE, vmcb->gs.base);
 951 }
 952
 953 void vcpu_park(void)
 954 {
 955         vcpu_vendor_reset(APIC_BSP_PSEUDO_SIPI);
 956         /* No need to clear VMCB Clean bit: vcpu_vendor_reset() already does
 957          * this. */
 958         this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
 959
 960         vcpu_tlb_flush();
 961 }
 962
 963 void vcpu_nmi_handler(void)
 964 {
 965 }
 966
 967 void vcpu_tlb_flush(void)
 968 {
 969         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 970
 971         if (has_flush_by_asid)
 972                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
 973         else
 974                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
 975 }
 976
 977 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
 978                               unsigned long pc, unsigned int *size)
 979 {
 980         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 981         unsigned long start;
 982
 983         if (has_assists) {
 984                 if (!*size)
 985                         return NULL;
 986                 start = vmcb->rip - pc;
 987                 if (start < vmcb->bytes_fetched) {
 988                         *size = vmcb->bytes_fetched - start;
 989                         return &vmcb->guest_bytes[start];
 990                 } else {
 991                         return NULL;
 992                 }
 993         } else {
 994                 return vcpu_map_inst(pg_structs, pc, size);
 995         }
 996 }
 997
 998 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
 999                                     struct vcpu_io_bitmap *iobm)
1000 {
1001         iobm->data = cell->arch.svm.iopm;
1002         iobm->size = IOPM_PAGES * PAGE_SIZE;
1003 }
1004
1005 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1006 {
1007         struct vmcb *vmcb = &this_cpu_data()->vmcb;
1008
1009         x_state->efer = vmcb->efer;
1010         x_state->rflags = vmcb->rflags;
1011         x_state->cs = vmcb->cs.selector;
1012         x_state->rip = vmcb->rip;
1013 }
1014
1015 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1016 void enable_irq(void)
1017 {
1018         asm volatile("stgi; sti" : : : "memory");
1019 }
1020
1021 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1022 void disable_irq(void)
1023 {
1024         asm volatile("cli; clgi" : : : "memory");
1025 }