hypervisor/arch/arm/irqchip.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) ARM Limited, 2014
   5  *
   6  * Authors:
   7  *  Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include <jailhouse/entry.h>
  14 #include <jailhouse/mmio.h>
  15 #include <jailhouse/paging.h>
  16 #include <jailhouse/printk.h>
  17 #include <jailhouse/string.h>
  18 #include <asm/gic_common.h>
  19 #include <asm/irqchip.h>
  20 #include <asm/platform.h>
  21 #include <asm/setup.h>
  22 #include <asm/sysregs.h>
  23
  24 /* AMBA's biosfood */
  25 #define AMBA_DEVICE     0xb105f00d
  26
  27 void *gicd_base;
  28 unsigned long gicd_size;
  29
  30 /*
  31  * The init function must be called after the MMU setup, and whilst in the
  32  * per-cpu setup, which means that a bool must be set by the master CPU
  33  */
  34 static bool irqchip_is_init;
  35 static struct irqchip_ops irqchip;
  36
  37 bool spi_in_cell(struct cell *cell, unsigned int spi)
  38 {
  39         /* FIXME: Change the configuration to a bitmask range */
  40         u32 spi_mask;
  41
  42         if (spi >= 64)
  43                 return false;
  44         else if (spi >= 32)
  45                 spi_mask = cell->arch.spis >> 32;
  46         else
  47                 spi_mask = cell->arch.spis;
  48
  49         return spi_mask & (1 << (spi & 31));
  50 }
  51
  52 void irqchip_set_pending(struct per_cpu *cpu_data, u16 irq_id, bool try_inject)
  53 {
  54         unsigned int new_tail;
  55
  56         if (try_inject && irqchip.inject_irq(cpu_data, irq_id) != -EBUSY)
  57                 return;
  58
  59         spin_lock(&cpu_data->pending_irqs_lock);
  60
  61         new_tail = (cpu_data->pending_irqs_tail + 1) % MAX_PENDING_IRQS;
  62
  63         /* Queue space available? */
  64         if (new_tail != cpu_data->pending_irqs_head) {
  65                 cpu_data->pending_irqs[cpu_data->pending_irqs_tail] = irq_id;
  66                 cpu_data->pending_irqs_tail = new_tail;
  67                 /*
  68                  * Make the change to pending_irqs_tail visible before the
  69                  * caller sends SGI_INJECT.
  70                  */
  71                 memory_barrier();
  72         }
  73
  74         spin_unlock(&cpu_data->pending_irqs_lock);
  75 }
  76
  77 void irqchip_inject_pending(struct per_cpu *cpu_data)
  78 {
  79         u16 irq_id;
  80
  81         while (cpu_data->pending_irqs_head != cpu_data->pending_irqs_tail) {
  82                 irq_id = cpu_data->pending_irqs[cpu_data->pending_irqs_head];
  83
  84                 if (irqchip.inject_irq(cpu_data, irq_id) == -EBUSY) {
  85                         /*
  86                          * The list registers are full, trigger maintenance
  87                          * interrupt and leave.
  88                          */
  89                         irqchip.enable_maint_irq(true);
  90                         return;
  91                 }
  92
  93                 cpu_data->pending_irqs_head =
  94                         (cpu_data->pending_irqs_head + 1) % MAX_PENDING_IRQS;
  95         }
  96
  97         /*
  98          * The software interrupt queue is empty - turn off the maintenance
  99          * interrupt.
 100          */
 101         irqchip.enable_maint_irq(false);
 102 }
 103
 104 void irqchip_handle_irq(struct per_cpu *cpu_data)
 105 {
 106         irqchip.handle_irq(cpu_data);
 107 }
 108
 109 void irqchip_eoi_irq(u32 irqn, bool deactivate)
 110 {
 111         irqchip.eoi_irq(irqn, deactivate);
 112 }
 113
 114 int irqchip_send_sgi(struct sgi *sgi)
 115 {
 116         return irqchip.send_sgi(sgi);
 117 }
 118
 119 int irqchip_cpu_init(struct per_cpu *cpu_data)
 120 {
 121         if (irqchip.cpu_init)
 122                 return irqchip.cpu_init(cpu_data);
 123
 124         return 0;
 125 }
 126
 127 int irqchip_cpu_reset(struct per_cpu *cpu_data)
 128 {
 129         cpu_data->pending_irqs_head = cpu_data->pending_irqs_tail = 0;
 130
 131         if (irqchip.cpu_reset)
 132                 return irqchip.cpu_reset(cpu_data, false);
 133
 134         return 0;
 135 }
 136
 137 void irqchip_cpu_shutdown(struct per_cpu *cpu_data)
 138 {
 139         /*
 140          * The GIC backend must take care of only resetting the hyp interface if
 141          * it has been initialised: this function may be executed during the
 142          * setup phase.
 143          */
 144         if (irqchip.cpu_reset)
 145                 irqchip.cpu_reset(cpu_data, true);
 146 }
 147
 148 static const struct jailhouse_irqchip *
 149 irqchip_find_config(struct jailhouse_cell_desc *config)
 150 {
 151         const struct jailhouse_irqchip *irq_config =
 152                 jailhouse_cell_irqchips(config);
 153
 154         if (config->num_irqchips)
 155                 return irq_config;
 156         else
 157                 return NULL;
 158 }
 159
 160 int irqchip_cell_init(struct cell *cell)
 161 {
 162         const struct jailhouse_irqchip *pins = irqchip_find_config(cell->config);
 163
 164         cell->arch.spis = (pins ? pins->pin_bitmap : 0);
 165
 166         return irqchip.cell_init(cell);
 167 }
 168
 169 void irqchip_cell_exit(struct cell *cell)
 170 {
 171         const struct jailhouse_irqchip *root_pins =
 172                 irqchip_find_config(root_cell.config);
 173
 174         /* might be called by arch_shutdown while rolling back
 175          * a failed setup */
 176         if (!irqchip_is_init)
 177                 return;
 178
 179         if (root_pins)
 180                 root_cell.arch.spis |= cell->arch.spis & root_pins->pin_bitmap;
 181
 182         irqchip.cell_exit(cell);
 183 }
 184
 185 void irqchip_root_cell_shrink(struct cell *cell)
 186 {
 187         root_cell.arch.spis &= ~(cell->arch.spis);
 188 }
 189
 190 /* Only the GIC is implemented */
 191 extern struct irqchip_ops gic_irqchip;
 192
 193 int irqchip_init(void)
 194 {
 195         int i, err;
 196         u32 pidr2, cidr;
 197         u32 dev_id = 0;
 198
 199         /* Only executed on master CPU */
 200         if (irqchip_is_init)
 201                 return 0;
 202
 203         /* FIXME: parse device tree */
 204         gicd_base = GICD_BASE;
 205         gicd_size = GICD_SIZE;
 206
 207         if ((err = arch_map_device(gicd_base, gicd_base, gicd_size)) != 0)
 208                 return err;
 209
 210         for (i = 3; i >= 0; i--) {
 211                 cidr = mmio_read32(gicd_base + GICD_CIDR0 + i * 4);
 212                 dev_id |= cidr << i * 8;
 213         }
 214         if (dev_id != AMBA_DEVICE)
 215                 goto err_no_distributor;
 216
 217         /* Probe the GIC version */
 218         pidr2 = mmio_read32(gicd_base + GICD_PIDR2);
 219         switch (GICD_PIDR2_ARCH(pidr2)) {
 220         case 0x2:
 221         case 0x3:
 222         case 0x4:
 223                 memcpy(&irqchip, &gic_irqchip, sizeof(struct irqchip_ops));
 224                 break;
 225         }
 226
 227         if (irqchip.init) {
 228                 err = irqchip.init();
 229                 irqchip_is_init = true;
 230
 231                 return err;
 232         }
 233
 234 err_no_distributor:
 235         printk("GIC: no distributor found\n");
 236         arch_unmap_device(gicd_base, gicd_size);
 237
 238         return -ENODEV;
 239 }