2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) ARM Limited, 2014
7 * Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #include <jailhouse/control.h>
14 #include <jailhouse/mmio.h>
15 #include <jailhouse/printk.h>
16 #include <jailhouse/processor.h>
17 #include <jailhouse/types.h>
18 #include <asm/control.h>
19 #include <asm/gic_common.h>
20 #include <asm/irqchip.h>
21 #include <asm/platform.h>
22 #include <asm/setup.h>
23 #include <asm/traps.h>
26 * This implementation assumes that the kernel driver already initialised most
28 * There is almost no instruction barrier, since IRQs are always disabled in the
29 * hyp, and ERET serves as the context synchronization event.
32 static unsigned int gic_num_lr;
33 static unsigned int gic_num_priority_bits;
34 static u32 gic_version;
36 extern void *gicd_base;
37 extern unsigned int gicd_size;
38 static void *gicr_base;
39 static unsigned int gicr_size;
41 static int gic_init(void)
45 /* FIXME: parse a dt */
46 gicr_base = GICR_BASE;
47 gicr_size = GICR_SIZE;
49 /* Let the per-cpu code access the redistributors */
50 err = arch_map_device(gicr_base, gicr_base, gicr_size);
55 static void gic_clear_pending_irqs(void)
59 /* Clear list registers. */
60 for (n = 0; n < gic_num_lr; n++)
63 /* Clear active priority bits */
64 if (gic_num_priority_bits >= 5)
65 arm_write_sysreg(ICH_AP1R0_EL2, 0);
66 if (gic_num_priority_bits >= 6)
67 arm_write_sysreg(ICH_AP1R1_EL2, 0);
68 if (gic_num_priority_bits > 6) {
69 arm_write_sysreg(ICH_AP1R2_EL2, 0);
70 arm_write_sysreg(ICH_AP1R3_EL2, 0);
74 static int gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
77 void *gicr = cpu_data->gicr_base;
79 bool root_shutdown = is_shutdown && (cpu_data->cell == &root_cell);
85 gic_clear_pending_irqs();
87 gicr += GICR_SGI_BASE;
88 active = mmio_read32(gicr + GICR_ICACTIVER);
89 /* Deactivate all active PPIs */
90 for (i = 16; i < 32; i++) {
91 if (test_bit(i, &active))
92 arm_write_sysreg(ICC_DIR_EL1, i);
96 * Disable all PPIs, ensure IPIs are enabled.
97 * On shutdown, the root cell expects to find all its PPIs still enabled
98 * when returning to the driver.
101 mmio_write32(gicr + GICR_ICENABLER, 0xffff0000);
102 mmio_write32(gicr + GICR_ISENABLER, 0x0000ffff);
105 /* Restore the root config */
106 arm_read_sysreg(ICH_VMCR_EL2, ich_vmcr);
108 if (!(ich_vmcr & ICH_VMCR_VEOIM)) {
110 arm_read_sysreg(ICC_CTLR_EL1, icc_ctlr);
111 icc_ctlr &= ~ICC_CTLR_EOImode;
112 arm_write_sysreg(ICC_CTLR_EL1, icc_ctlr);
115 arm_write_sysreg(ICH_HCR_EL2, 0);
118 arm_write_sysreg(ICH_VMCR_EL2, 0);
123 static int gic_cpu_init(struct per_cpu *cpu_data)
127 u32 cell_icc_ctlr, cell_icc_pmr, cell_icc_igrpen1;
130 void *redist_base = gicr_base;
132 /* Find redistributor */
134 pidr = mmio_read32(redist_base + GICR_PIDR2);
135 gic_version = GICR_PIDR2_ARCH(pidr);
136 if (gic_version != 3 && gic_version != 4)
139 typer = mmio_read64(redist_base + GICR_TYPER);
140 if ((typer >> 32) == cpu_data->cpu_id) {
141 cpu_data->gicr_base = redist_base;
145 redist_base += 0x20000;
146 if (gic_version == 4)
147 redist_base += 0x20000;
148 } while (!(typer & GICR_TYPER_Last));
150 if (cpu_data->gicr_base == 0) {
151 printk("GIC: No redist found for CPU%d\n", cpu_data->cpu_id);
155 /* Ensure all IPIs are enabled */
156 mmio_write32(redist_base + GICR_SGI_BASE + GICR_ISENABLER, 0x0000ffff);
160 * This allow to drop the priority of level-triggered interrupts without
161 * deactivating them, and thus ensure that they won't be immediately
162 * re-triggered. (e.g. timer)
163 * They can then be injected into the guest using the LR.HW bit, and
164 * will be deactivated once the guest does an EOI after handling the
167 arm_read_sysreg(ICC_CTLR_EL1, cell_icc_ctlr);
168 arm_write_sysreg(ICC_CTLR_EL1, ICC_CTLR_EOImode);
170 arm_read_sysreg(ICC_PMR_EL1, cell_icc_pmr);
171 arm_write_sysreg(ICC_PMR_EL1, ICC_PMR_DEFAULT);
173 arm_read_sysreg(ICC_IGRPEN1_EL1, cell_icc_igrpen1);
174 arm_write_sysreg(ICC_IGRPEN1_EL1, ICC_IGRPEN1_EN);
176 arm_read_sysreg(ICH_VTR_EL2, ich_vtr);
177 gic_num_lr = (ich_vtr & 0xf) + 1;
178 gic_num_priority_bits = (ich_vtr >> 29) + 1;
181 * Clear pending virtual IRQs in case anything is left from previous
182 * use. Physically pending IRQs will be forwarded to Linux once we
183 * enable interrupts for the hypervisor.
185 gic_clear_pending_irqs();
187 ich_vmcr = (cell_icc_pmr & ICC_PMR_MASK) << ICH_VMCR_VPMR_SHIFT;
188 if (cell_icc_igrpen1 & ICC_IGRPEN1_EN)
189 ich_vmcr |= ICH_VMCR_VENG1;
190 if (cell_icc_ctlr & ICC_CTLR_EOImode)
191 ich_vmcr |= ICH_VMCR_VEOIM;
192 arm_write_sysreg(ICH_VMCR_EL2, ich_vmcr);
194 /* After this, the cells access the virtual interface of the GIC. */
195 arm_write_sysreg(ICH_HCR_EL2, ICH_HCR_EN);
200 static void gic_route_spis(struct cell *config_cell, struct cell *dest_cell)
203 void *irouter = gicd_base + GICD_IROUTER;
204 unsigned int first_cpu;
206 /* Use the core functions to retrieve the first physical id */
207 for_each_cpu(first_cpu, dest_cell->cpu_set)
210 for (i = 0; i < 64; i++, irouter += 8) {
211 if (spi_in_cell(config_cell, i))
212 mmio_write64(irouter, first_cpu);
216 static int gic_handle_redist_access(struct mmio_access *mmio)
218 struct cell *cell = this_cell();
221 int ret = TRAP_UNHANDLED;
222 unsigned int virt_id;
223 void *virt_redist = 0;
224 void *phys_redist = 0;
225 unsigned int redist_size = (gic_version == 4) ? 0x40000 : 0x20000;
226 void *address = (void *)mmio->address;
229 * The redistributor accessed by the cell is not the one stored in these
230 * cpu_datas, but the one associated to its virtual id. So we first
231 * need to translate the redistributor address.
233 for_each_cpu(cpu, cell->cpu_set) {
234 virt_id = arm_cpu_phys2virt(cpu);
235 virt_redist = per_cpu(virt_id)->gicr_base;
236 if (address >= virt_redist && address < virt_redist
238 phys_redist = per_cpu(cpu)->gicr_base;
243 if (phys_redist == NULL)
244 return TRAP_FORBIDDEN;
246 reg = address - virt_redist;
247 mmio->address = (unsigned long)phys_redist + reg;
249 /* Change the ID register, all other accesses are allowed. */
250 if (!mmio->is_write) {
253 if (virt_id == cell->arch.last_virt_id)
254 mmio->value = GICR_TYPER_Last;
257 /* AArch64 can use a writeq for this register */
259 mmio->value |= (u64)virt_id << 32;
264 /* Upper bits contain the affinity */
265 mmio->value = virt_id;
270 if (ret == TRAP_HANDLED)
273 arm_mmio_perform_access(mmio);
277 static int gic_cell_init(struct cell *cell)
279 gic_route_spis(cell, cell);
283 static void gic_cell_exit(struct cell *cell)
285 /* Reset interrupt routing of the cell's spis*/
286 gic_route_spis(cell, &root_cell);
289 static int gic_send_sgi(struct sgi *sgi)
292 u16 targets = sgi->targets;
294 if (!is_sgi(sgi->id))
297 if (sgi->routing_mode == 2)
298 targets = 1 << phys_processor_id();
300 val = (u64)sgi->aff3 << ICC_SGIR_AFF3_SHIFT
301 | (u64)sgi->aff2 << ICC_SGIR_AFF2_SHIFT
302 | sgi->aff1 << ICC_SGIR_AFF1_SHIFT
303 | (targets & ICC_SGIR_TARGET_MASK)
304 | (sgi->id & 0xf) << ICC_SGIR_IRQN_SHIFT;
306 if (sgi->routing_mode == 1)
307 val |= ICC_SGIR_ROUTING_BIT;
310 * Ensure the targets see our modifications to their per-cpu
315 arm_write_sysreg(ICC_SGI1R_EL1, val);
321 void gicv3_handle_sgir_write(u64 sgir)
324 unsigned long routing_mode = !!(sgir & ICC_SGIR_ROUTING_BIT);
326 /* FIXME: clusters are not supported yet. */
327 sgi.targets = sgir & ICC_SGIR_TARGET_MASK;
328 sgi.routing_mode = routing_mode;
329 sgi.aff1 = sgir >> ICC_SGIR_AFF1_SHIFT & 0xff;
330 sgi.aff2 = sgir >> ICC_SGIR_AFF2_SHIFT & 0xff;
331 sgi.aff3 = sgir >> ICC_SGIR_AFF3_SHIFT & 0xff;
332 sgi.id = sgir >> ICC_SGIR_IRQN_SHIFT & 0xf;
334 gic_handle_sgir_write(&sgi, true);
337 static void gic_eoi_irq(u32 irq_id, bool deactivate)
339 arm_write_sysreg(ICC_EOIR1_EL1, irq_id);
341 arm_write_sysreg(ICC_DIR_EL1, irq_id);
344 static int gic_inject_irq(struct per_cpu *cpu_data, struct pending_irq *irq)
351 arm_read_sysreg(ICH_ELSR_EL2, elsr);
352 for (i = 0; i < gic_num_lr; i++) {
353 if ((elsr >> i) & 1) {
354 /* Entry is invalid, candidate for injection */
361 * Entry is in use, check that it doesn't match the one we want
367 * A strict phys->virt id mapping is used for SPIs, so this test
368 * should be sufficient.
370 if ((u32)lr == irq->virt_id)
377 * All list registers are in use, trigger a maintenance
378 * interrupt once they are available again.
380 arm_read_sysreg(ICH_HCR_EL2, hcr);
382 arm_write_sysreg(ICH_HCR_EL2, hcr);
388 /* Only group 1 interrupts */
389 lr |= ICH_LR_GROUP_BIT;
390 lr |= ICH_LR_PENDING;
393 lr |= (u64)irq->type.irq << ICH_LR_PHYS_ID_SHIFT;
394 } else if (irq->type.sgi.maintenance) {
395 lr |= ICH_LR_SGI_EOI;
398 gic_write_lr(free_lr, lr);
403 static int gic_mmio_access(struct mmio_access *mmio)
405 void *address = (void *)mmio->address;
407 if (address >= gicd_base && address < gicd_base + gicd_size)
408 return gic_handle_dist_access(mmio);
410 if (address >= gicr_base && address < gicr_base + gicr_size)
411 return gic_handle_redist_access(mmio);
413 return TRAP_UNHANDLED;
416 struct irqchip_ops gic_irqchip = {
418 .cpu_init = gic_cpu_init,
419 .cpu_reset = gic_cpu_reset,
420 .cell_init = gic_cell_init,
421 .cell_exit = gic_cell_exit,
422 .send_sgi = gic_send_sgi,
423 .handle_irq = gic_handle_irq,
424 .inject_irq = gic_inject_irq,
425 .eoi_irq = gic_eoi_irq,
426 .mmio_access = gic_mmio_access,