hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 static bool has_avic, has_assists, has_flush_by_asid;
  43
  44 static const struct segment invalid_seg;
  45
  46 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  47
  48 /* bit cleared: direct access allowed */
  49 // TODO: convert to whitelist
  50 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  51         [ SVM_MSRPM_0000 ] = {
  52                 [      0/4 ...  0x017/4 ] = 0,
  53                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  54                 [  0x01c/4 ...  0x1ff/4 ] = 0,
  55                 [  0x200/4 ...  0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
  56                 [  0x274/4 ...  0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
  57                 [  0x278/4 ...  0x2fb/4 ] = 0,
  58                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  59                 [  0x300/4 ...  0x7ff/4 ] = 0,
  60                 /* x2APIC MSRs - emulated if not present */
  61                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  62                 [  0x804/4 ...  0x807/4 ] = 0,
  63                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  64                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  65                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  66                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  67                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  68                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  69                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  70                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  71                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  72                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  73                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  74                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  75                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  76                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  77                 [  0x840/4 ... 0x1fff/4 ] = 0,
  78         },
  79         [ SVM_MSRPM_C000 ] = {
  80                 [      0/4 ...  0x07f/4 ] = 0,
  81                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  82                 [  0x084/4 ... 0x1fff/4 ] = 0
  83         },
  84         [ SVM_MSRPM_C001 ] = {
  85                 [      0/4 ... 0x1fff/4 ] = 0,
  86         },
  87         [ SVM_MSRPM_RESV ] = {
  88                 [      0/4 ... 0x1fff/4 ] = 0,
  89         }
  90 };
  91
  92 /* This page is mapped so the code begins at 0x000ffff0 */
  93 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  94         [0xff0] = 0xfa, /* 1: cli */
  95         [0xff1] = 0xf4, /*    hlt */
  96         [0xff2] = 0xeb,
  97         [0xff3] = 0xfc  /*    jmp 1b */
  98 };
  99
 100 static void *parked_mode_npt;
 101
 102 static void *avic_page;
 103
 104 static int svm_check_features(void)
 105 {
 106         /* SVM is available */
 107         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 108                 return trace_error(-ENODEV);
 109
 110         /* Nested paging */
 111         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 112                 return trace_error(-EIO);
 113
 114         /* Decode assists */
 115         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 116                 has_assists = true;
 117
 118         /* AVIC support */
 119         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 120                 has_avic = true;
 121
 122         /* TLB Flush by ASID support */
 123         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 124                 has_flush_by_asid = true;
 125
 126         return 0;
 127 }
 128
 129 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 130                                      const struct desc_table_reg *dtr)
 131 {
 132         struct svm_segment tmp = { 0 };
 133
 134         if (dtr) {
 135                 tmp.base = dtr->base;
 136                 tmp.limit = dtr->limit & 0xffff;
 137         }
 138
 139         *svm_segment = tmp;
 140 }
 141
 142 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
 143 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 144                                          const struct segment *segment)
 145 {
 146         u32 ar;
 147
 148         svm_segment->selector = segment->selector;
 149
 150         if (segment->access_rights == 0x10000) {
 151                 svm_segment->access_rights = 0;
 152         } else {
 153                 ar = segment->access_rights;
 154                 svm_segment->access_rights =
 155                         ((ar & 0xf000) >> 4) | (ar & 0x00ff);
 156         }
 157
 158         svm_segment->limit = segment->limit;
 159         svm_segment->base = segment->base;
 160 }
 161
 162 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 163 {
 164         /* No real need for this function; used for consistency with vmx.c */
 165         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 166         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 167
 168         return true;
 169 }
 170
 171 static int vmcb_setup(struct per_cpu *cpu_data)
 172 {
 173         struct vmcb *vmcb = &cpu_data->vmcb;
 174
 175         memset(vmcb, 0, sizeof(struct vmcb));
 176
 177         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 178         vmcb->cr3 = cpu_data->linux_cr3;
 179         vmcb->cr4 = cpu_data->linux_cr4;
 180
 181         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 182         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 183         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 184         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 185         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 186         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 187         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 188
 189         set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
 190         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 191         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 192
 193         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 194
 195         vmcb->rflags = 0x02;
 196         /* Indicate success to the caller of arch_entry */
 197         vmcb->rax = 0;
 198         vmcb->rsp = cpu_data->linux_sp +
 199                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 200         vmcb->rip = cpu_data->linux_ip;
 201
 202         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 203         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 204         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 205         vmcb->star = read_msr(MSR_STAR);
 206         vmcb->lstar = read_msr(MSR_LSTAR);
 207         vmcb->cstar = read_msr(MSR_CSTAR);
 208         vmcb->sfmask = read_msr(MSR_SFMASK);
 209         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 210
 211         vmcb->dr6 = 0x00000ff0;
 212         vmcb->dr7 = 0x00000400;
 213
 214         /* Make the hypervisor visible */
 215         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 216
 217         vmcb->g_pat = cpu_data->pat;
 218
 219         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 220         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 221         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 222         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 223         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 224
 225         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 226         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 227
 228         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 229
 230         vmcb->np_enable = 1;
 231         /* No more than one guest owns the CPU */
 232         vmcb->guest_asid = 1;
 233
 234         /* TODO: Setup AVIC */
 235
 236         /* Explicitly mark all of the state as new */
 237         vmcb->clean_bits = 0;
 238
 239         return svm_set_cell_config(cpu_data->cell, vmcb);
 240 }
 241
 242 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 243                                      unsigned long gphys,
 244                                      unsigned long flags)
 245 {
 246         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 247                         gphys, flags);
 248 }
 249
 250 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 251 {
 252         /* See APMv2, Section 15.25.5 */
 253         *pte = (next_pt & 0x000ffffffffff000UL) |
 254                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 255 }
 256
 257 int vcpu_vendor_init(void)
 258 {
 259         struct paging_structures parking_pt;
 260         unsigned long vm_cr;
 261         int err, n;
 262
 263         err = svm_check_features();
 264         if (err)
 265                 return err;
 266
 267         vm_cr = read_msr(MSR_VM_CR);
 268         if (vm_cr & VM_CR_SVMDIS)
 269                 /* SVM disabled in BIOS */
 270                 return trace_error(-EPERM);
 271
 272         /* Nested paging is the same as the native one */
 273         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 274         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 275                 npt_paging[n].set_next_pt = npt_set_next_pt;
 276
 277         /* Map guest parking code (shared between cells and CPUs) */
 278         parking_pt.root_paging = npt_paging;
 279         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 280         if (!parked_mode_npt)
 281                 return -ENOMEM;
 282         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 283                             PAGE_SIZE, 0x000ff000,
 284                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 285                             PAGING_NON_COHERENT);
 286         if (err)
 287                 return err;
 288
 289         /* This is always false for AMD now (except in nested SVM);
 290            see Sect. 16.3.1 in APMv2 */
 291         if (using_x2apic) {
 292                 /* allow direct x2APIC access except for ICR writes */
 293                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 294                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 295                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 296         } else {
 297                 if (has_avic) {
 298                         avic_page = page_alloc(&remap_pool, 1);
 299                         if (!avic_page)
 300                                 return trace_error(-ENOMEM);
 301                 }
 302         }
 303
 304         return vcpu_cell_init(&root_cell);
 305 }
 306
 307 int vcpu_vendor_cell_init(struct cell *cell)
 308 {
 309         u64 flags;
 310         int err;
 311
 312         /* allocate iopm (two 4-K pages + 3 bits) */
 313         cell->svm.iopm = page_alloc(&mem_pool, 3);
 314         if (!cell->svm.iopm)
 315                 return -ENOMEM;
 316
 317         /* build root NPT of cell */
 318         cell->svm.npt_structs.root_paging = npt_paging;
 319         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 320         if (!cell->svm.npt_structs.root_table)
 321                 return -ENOMEM;
 322
 323         if (!has_avic) {
 324                 /*
 325                  * Map xAPIC as is; reads are passed, writes are trapped.
 326                  */
 327                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 328                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 329                                     PAGE_SIZE, XAPIC_BASE,
 330                                     flags,
 331                                     PAGING_NON_COHERENT);
 332         } else {
 333                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 334                 err = paging_create(&cell->svm.npt_structs,
 335                                     paging_hvirt2phys(avic_page),
 336                                     PAGE_SIZE, XAPIC_BASE,
 337                                     flags,
 338                                     PAGING_NON_COHERENT);
 339         }
 340
 341         return err;
 342 }
 343
 344 int vcpu_map_memory_region(struct cell *cell,
 345                            const struct jailhouse_memory *mem)
 346 {
 347         u64 phys_start = mem->phys_start;
 348         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 349
 350         if (mem->flags & JAILHOUSE_MEM_READ)
 351                 flags |= PAGE_FLAG_PRESENT;
 352         if (mem->flags & JAILHOUSE_MEM_WRITE)
 353                 flags |= PAGE_FLAG_RW;
 354         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 355                 flags |= PAGE_FLAG_NOEXECUTE;
 356         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 357                 phys_start = paging_hvirt2phys(&cell->comm_page);
 358
 359         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 360                              mem->virt_start, flags, PAGING_NON_COHERENT);
 361 }
 362
 363 int vcpu_unmap_memory_region(struct cell *cell,
 364                              const struct jailhouse_memory *mem)
 365 {
 366         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 367                               mem->size, PAGING_NON_COHERENT);
 368 }
 369
 370 void vcpu_vendor_cell_exit(struct cell *cell)
 371 {
 372         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 373                        PAGING_NON_COHERENT);
 374         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 375 }
 376
 377 int vcpu_init(struct per_cpu *cpu_data)
 378 {
 379         unsigned long efer;
 380         int err;
 381
 382         err = svm_check_features();
 383         if (err)
 384                 return err;
 385
 386         efer = read_msr(MSR_EFER);
 387         if (efer & EFER_SVME)
 388                 return trace_error(-EBUSY);
 389
 390         efer |= EFER_SVME;
 391         write_msr(MSR_EFER, efer);
 392
 393         cpu_data->svm_state = SVMON;
 394
 395         if (!vmcb_setup(cpu_data))
 396                 return trace_error(-EIO);
 397
 398         /*
 399          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 400          * set the values of reserved bits to the values found during the
 401          * previous CR0 read."
 402          * But we want to avoid surprises with new features unknown to us but
 403          * set by Linux. So check if any assumed revered bit was set and bail
 404          * out if so.
 405          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 406          */
 407         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 408                 return -EIO;
 409
 410         /* bring CR0 and CR4 into well-defined states */
 411         write_cr0(X86_CR0_HOST_STATE);
 412         write_cr4(X86_CR4_HOST_STATE);
 413
 414         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 415
 416         return 0;
 417 }
 418
 419 void vcpu_exit(struct per_cpu *cpu_data)
 420 {
 421         unsigned long efer;
 422
 423         if (cpu_data->svm_state == SVMOFF)
 424                 return;
 425
 426         cpu_data->svm_state = SVMOFF;
 427
 428         /* We are leaving - set the GIF */
 429         asm volatile ("stgi" : : : "memory");
 430
 431         efer = read_msr(MSR_EFER);
 432         efer &= ~EFER_SVME;
 433         write_msr(MSR_EFER, efer);
 434
 435         write_msr(MSR_VM_HSAVE_PA, 0);
 436 }
 437
 438 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 439 {
 440         unsigned long vmcb_pa, host_stack;
 441
 442         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 443         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 444
 445         /* We enter Linux at the point arch_entry would return to as well.
 446          * rax is cleared to signal success to the caller. */
 447         asm volatile(
 448                 "clgi\n\t"
 449                 "mov (%%rdi),%%r15\n\t"
 450                 "mov 0x8(%%rdi),%%r14\n\t"
 451                 "mov 0x10(%%rdi),%%r13\n\t"
 452                 "mov 0x18(%%rdi),%%r12\n\t"
 453                 "mov 0x20(%%rdi),%%rbx\n\t"
 454                 "mov 0x28(%%rdi),%%rbp\n\t"
 455                 "mov %0, %%rax\n\t"
 456                 "vmload %%rax\n\t"
 457                 "vmrun %%rax\n\t"
 458                 "vmsave %%rax\n\t"
 459                 /* Restore hypervisor stack */
 460                 "mov %2, %%rsp\n\t"
 461                 "jmp svm_vmexit"
 462                 : /* no output */
 463                 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
 464                 : "memory", "r15", "r14", "r13", "r12",
 465                   "rbx", "rbp", "rax", "cc");
 466         __builtin_unreachable();
 467 }
 468
 469 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
 470 {
 471         struct per_cpu *cpu_data = this_cpu_data();
 472         struct vmcb *vmcb = &cpu_data->vmcb;
 473         unsigned long *stack = (unsigned long *)vmcb->rsp;
 474         unsigned long linux_ip = vmcb->rip;
 475
 476         /*
 477          * Restore the MSRs.
 478          *
 479          * XXX: One could argue this is better to be done in
 480          * arch_cpu_restore(), however, it would require changes
 481          * to cpu_data to store STAR and friends.
 482          */
 483         write_msr(MSR_STAR, vmcb->star);
 484         write_msr(MSR_LSTAR, vmcb->lstar);
 485         write_msr(MSR_CSTAR, vmcb->cstar);
 486         write_msr(MSR_SFMASK, vmcb->sfmask);
 487         write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
 488
 489         cpu_data->linux_cr0 = vmcb->cr0;
 490         cpu_data->linux_cr3 = vmcb->cr3;
 491
 492         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 493         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 494         cpu_data->linux_idtr.base = vmcb->idtr.base;
 495         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 496
 497         cpu_data->linux_cs.selector = vmcb->cs.selector;
 498
 499         cpu_data->linux_tss.selector = vmcb->tr.selector;
 500
 501         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 502         cpu_data->linux_fs.base = vmcb->fs.base;
 503         cpu_data->linux_gs.base = vmcb->gs.base;
 504
 505         cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
 506         cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
 507         cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
 508
 509         cpu_data->linux_ds.selector = vmcb->ds.selector;
 510         cpu_data->linux_es.selector = vmcb->es.selector;
 511         cpu_data->linux_fs.selector = vmcb->fs.selector;
 512         cpu_data->linux_gs.selector = vmcb->gs.selector;
 513
 514         arch_cpu_restore(cpu_data, 0);
 515
 516         stack--;
 517         *stack = linux_ip;
 518
 519         asm volatile (
 520                 "mov %%rbx,%%rsp\n\t"
 521                 "pop %%r15\n\t"
 522                 "pop %%r14\n\t"
 523                 "pop %%r13\n\t"
 524                 "pop %%r12\n\t"
 525                 "pop %%r11\n\t"
 526                 "pop %%r10\n\t"
 527                 "pop %%r9\n\t"
 528                 "pop %%r8\n\t"
 529                 "pop %%rdi\n\t"
 530                 "pop %%rsi\n\t"
 531                 "pop %%rbp\n\t"
 532                 "add $8,%%rsp\n\t"
 533                 "pop %%rbx\n\t"
 534                 "pop %%rdx\n\t"
 535                 "pop %%rcx\n\t"
 536                 "mov %%rax,%%rsp\n\t"
 537                 "xor %%rax,%%rax\n\t"
 538                 "ret"
 539                 : : "a" (stack), "b" (&cpu_data->guest_regs));
 540         __builtin_unreachable();
 541 }
 542
 543 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 544 {
 545         struct vmcb *vmcb = &cpu_data->vmcb;
 546         unsigned long val;
 547         bool ok = true;
 548
 549         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 550         vmcb->cr3 = 0;
 551         vmcb->cr4 = 0;
 552
 553         vmcb->rflags = 0x02;
 554
 555         val = 0;
 556         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 557                 val = 0xfff0;
 558                 sipi_vector = 0xf0;
 559         }
 560         vmcb->rip = val;
 561         vmcb->rsp = 0;
 562
 563         vmcb->cs.selector = sipi_vector << 8;
 564         vmcb->cs.base = sipi_vector << 12;
 565         vmcb->cs.limit = 0xffff;
 566         vmcb->cs.access_rights = 0x009b;
 567
 568         vmcb->ds.selector = 0;
 569         vmcb->ds.base = 0;
 570         vmcb->ds.limit = 0xffff;
 571         vmcb->ds.access_rights = 0x0093;
 572
 573         vmcb->es.selector = 0;
 574         vmcb->es.base = 0;
 575         vmcb->es.limit = 0xffff;
 576         vmcb->es.access_rights = 0x0093;
 577
 578         vmcb->fs.selector = 0;
 579         vmcb->fs.base = 0;
 580         vmcb->fs.limit = 0xffff;
 581         vmcb->fs.access_rights = 0x0093;
 582
 583         vmcb->gs.selector = 0;
 584         vmcb->gs.base = 0;
 585         vmcb->gs.limit = 0xffff;
 586         vmcb->gs.access_rights = 0x0093;
 587
 588         vmcb->ss.selector = 0;
 589         vmcb->ss.base = 0;
 590         vmcb->ss.limit = 0xffff;
 591         vmcb->ss.access_rights = 0x0093;
 592
 593         vmcb->tr.selector = 0;
 594         vmcb->tr.base = 0;
 595         vmcb->tr.limit = 0xffff;
 596         vmcb->tr.access_rights = 0x008b;
 597
 598         vmcb->ldtr.selector = 0;
 599         vmcb->ldtr.base = 0;
 600         vmcb->ldtr.limit = 0xffff;
 601         vmcb->ldtr.access_rights = 0x0082;
 602
 603         vmcb->gdtr.selector = 0;
 604         vmcb->gdtr.base = 0;
 605         vmcb->gdtr.limit = 0xffff;
 606         vmcb->gdtr.access_rights = 0;
 607
 608         vmcb->idtr.selector = 0;
 609         vmcb->idtr.base = 0;
 610         vmcb->idtr.limit = 0xffff;
 611         vmcb->idtr.access_rights = 0;
 612
 613         vmcb->efer = EFER_SVME;
 614
 615         /* These MSRs are undefined on reset */
 616         vmcb->star = 0;
 617         vmcb->lstar = 0;
 618         vmcb->cstar = 0;
 619         vmcb->sfmask = 0;
 620         vmcb->sysenter_cs = 0;
 621         vmcb->sysenter_eip = 0;
 622         vmcb->sysenter_esp = 0;
 623         vmcb->kerngsbase = 0;
 624
 625         vmcb->dr7 = 0x00000400;
 626
 627         /* Almost all of the guest state changed */
 628         vmcb->clean_bits = 0;
 629
 630         ok &= svm_set_cell_config(cpu_data->cell, vmcb);
 631
 632         /* This is always false, but to be consistent with vmx.c... */
 633         if (!ok) {
 634                 panic_printk("FATAL: CPU reset failed\n");
 635                 panic_stop();
 636         }
 637 }
 638
 639 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 640 {
 641         this_cpu_data()->vmcb.rip += inst_len;
 642 }
 643
 644 static void update_efer(struct vmcb *vmcb)
 645 {
 646         unsigned long efer = vmcb->efer;
 647
 648         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 649                 return;
 650
 651         efer |= EFER_LMA;
 652
 653         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 654         if ((vmcb->efer ^ efer) & EFER_LMA)
 655                 vcpu_tlb_flush();
 656
 657         vmcb->efer = efer;
 658         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 659 }
 660
 661 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 662 {
 663         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 664
 665         if (vmcb->efer & EFER_LMA) {
 666                 pg_structs->root_paging = x86_64_paging;
 667                 pg_structs->root_table_gphys =
 668                         vmcb->cr3 & 0x000ffffffffff000UL;
 669         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 670                    !(vmcb->cr4 & X86_CR4_PAE)) {
 671                 pg_structs->root_paging = i386_paging;
 672                 pg_structs->root_table_gphys =
 673                         vmcb->cr3 & 0xfffff000UL;
 674         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 675                 /*
 676                  * Can be in non-paged protected mode as well, but
 677                  * the translation mechanism will stay the same ayway.
 678                  */
 679                 pg_structs->root_paging = realmode_paging;
 680                 /*
 681                  * This will make paging_get_guest_pages map the page
 682                  * that also contains the bootstrap code and, thus, is
 683                  * always present in a cell.
 684                  */
 685                 pg_structs->root_table_gphys = 0xff000;
 686         } else {
 687                 printk("FATAL: Unsupported paging mode\n");
 688                 return false;
 689         }
 690         return true;
 691 }
 692
 693 void vcpu_vendor_set_guest_pat(unsigned long val)
 694 {
 695         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 696
 697         vmcb->g_pat = val;
 698         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 699 }
 700
 701 struct parse_context {
 702         unsigned int remaining;
 703         unsigned int size;
 704         unsigned long cs_base;
 705         const u8 *inst;
 706 };
 707
 708 static bool ctx_advance(struct parse_context *ctx,
 709                         unsigned long *pc,
 710                         struct guest_paging_structures *pg_structs)
 711 {
 712         if (!ctx->size) {
 713                 ctx->size = ctx->remaining;
 714                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 715                                           &ctx->size);
 716                 if (!ctx->inst)
 717                         return false;
 718                 ctx->remaining -= ctx->size;
 719                 *pc += ctx->size;
 720         }
 721         return true;
 722 }
 723
 724 static bool svm_parse_mov_to_cr(struct vmcb *vmcb, unsigned long pc,
 725                                 unsigned char reg, unsigned long *gpr)
 726 {
 727         struct guest_paging_structures pg_structs;
 728         struct parse_context ctx = {};
 729         /* No prefixes are supported yet */
 730         u8 opcodes[] = {0x0f, 0x22}, modrm;
 731         bool ok = false;
 732         int n;
 733
 734         ctx.remaining = ARRAY_SIZE(opcodes);
 735         if (!vcpu_get_guest_paging_structs(&pg_structs))
 736                 goto out;
 737         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 738
 739         if (!ctx_advance(&ctx, &pc, &pg_structs))
 740                 goto out;
 741
 742         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
 743                 if (*(ctx.inst) != opcodes[n])
 744                         goto out;
 745                 if (!ctx_advance(&ctx, &pc, &pg_structs))
 746                         goto out;
 747         }
 748
 749         if (!ctx_advance(&ctx, &pc, &pg_structs))
 750                 goto out;
 751
 752         modrm = *(ctx.inst);
 753
 754         if (((modrm & 0x38) >> 3) != reg)
 755                 goto out;
 756
 757         if (gpr)
 758                 *gpr = (modrm & 0x7);
 759
 760         ok = true;
 761 out:
 762         return ok;
 763 }
 764
 765 /*
 766  * XXX: The only visible reason to have this function (vmx.c consistency
 767  * aside) is to prevent cells from setting invalid CD+NW combinations that
 768  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 769  * altogether?
 770  */
 771 static bool svm_handle_cr(struct per_cpu *cpu_data)
 772 {
 773         struct vmcb *vmcb = &cpu_data->vmcb;
 774         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 775         unsigned long reg = -1, val, bits;
 776         bool ok = true;
 777
 778         if (has_assists) {
 779                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 780                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 781                         ok = false;
 782                         goto out;
 783                 }
 784                 reg = vmcb->exitinfo1 & 0x07;
 785         } else {
 786                 if (!svm_parse_mov_to_cr(vmcb, vmcb->rip, 0, &reg)) {
 787                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 788                         ok = false;
 789                         goto out;
 790                 }
 791         };
 792
 793         if (reg == 4)
 794                 val = vmcb->rsp;
 795         else
 796                 val = cpu_data->guest_regs.by_index[15 - reg];
 797
 798         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 799         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 800         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 801         if ((val ^ vmcb->cr0) & bits)
 802                 vcpu_tlb_flush();
 803         /* TODO: better check for #GP reasons */
 804         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 805         if (val & X86_CR0_PG)
 806                 update_efer(vmcb);
 807         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 808
 809 out:
 810         return ok;
 811 }
 812
 813 static bool svm_handle_msr_write(struct per_cpu *cpu_data)
 814 {
 815         struct vmcb *vmcb = &cpu_data->vmcb;
 816         unsigned long efer;
 817
 818         if (cpu_data->guest_regs.rcx == MSR_EFER) {
 819                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 820                 efer = get_wrmsr_value(&cpu_data->guest_regs) | EFER_SVME;
 821                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 822                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 823                         vcpu_tlb_flush();
 824                 vmcb->efer = efer;
 825                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 826                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 827                 return true;
 828         }
 829
 830         return vcpu_handle_msr_write();
 831 }
 832
 833 /*
 834  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 835  * be treated separately in svm_handle_avic_access().
 836  */
 837 static bool svm_handle_apic_access(struct vmcb *vmcb)
 838 {
 839         struct guest_paging_structures pg_structs;
 840         unsigned int inst_len, offset;
 841         bool is_write;
 842
 843         /* The caller is responsible for sanity checks */
 844         is_write = !!(vmcb->exitinfo1 & 0x2);
 845         offset = vmcb->exitinfo2 - XAPIC_BASE;
 846
 847         if (offset & 0x00f)
 848                 goto out_err;
 849
 850         if (!vcpu_get_guest_paging_structs(&pg_structs))
 851                 goto out_err;
 852
 853         inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
 854                                     is_write);
 855         if (!inst_len)
 856                 goto out_err;
 857
 858         vcpu_skip_emulated_instruction(inst_len);
 859         return true;
 860
 861 out_err:
 862         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 863                      offset, is_write);
 864         return false;
 865 }
 866
 867 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
 868 {
 869         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 870                      vmcb->rsp, vmcb->rflags);
 871         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 872                      guest_regs->rbx, guest_regs->rcx);
 873         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 874                      guest_regs->rsi, guest_regs->rdi);
 875         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 876                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 877                      !!(vmcb->efer & EFER_LMA));
 878         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 879                      vmcb->cr3, vmcb->cr4);
 880         panic_printk("EFER: %p\n", vmcb->efer);
 881 }
 882
 883 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
 884 {
 885         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 886         u64 exitinfo = vmcb->exitinfo1;
 887
 888         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 889         io->port = (exitinfo >> 16) & 0xFFFF;
 890         io->size = (exitinfo >> 4) & 0x7;
 891         io->in = !!(exitinfo & 0x1);
 892         io->inst_len = vmcb->exitinfo2 - vmcb->rip;
 893         io->rep_or_str = !!(exitinfo & 0x0c);
 894 }
 895
 896 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
 897 {
 898         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 899
 900         mmio->phys_addr = vmcb->exitinfo2;
 901         mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
 902 }
 903
 904 void vcpu_handle_exit(struct per_cpu *cpu_data)
 905 {
 906         union registers *guest_regs = &cpu_data->guest_regs;
 907         struct vmcb *vmcb = &cpu_data->vmcb;
 908         bool res = false;
 909         int sipi_vector;
 910
 911         /* Restore GS value expected by per_cpu data accessors */
 912         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 913
 914         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 915         /*
 916          * All guest state is marked unmodified; individual handlers must clear
 917          * the bits as needed.
 918          */
 919         vmcb->clean_bits = 0xffffffff;
 920
 921         switch (vmcb->exitcode) {
 922         case VMEXIT_INVALID:
 923                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 924                              vmcb->exitcode);
 925                 break;
 926         case VMEXIT_NMI:
 927                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 928                 /* Temporarily enable GIF to consume pending NMI */
 929                 asm volatile("stgi; clgi" : : : "memory");
 930                 sipi_vector = x86_handle_events(cpu_data);
 931                 if (sipi_vector >= 0) {
 932                         printk("CPU %d received SIPI, vector %x\n",
 933                                cpu_data->cpu_id, sipi_vector);
 934                         svm_vcpu_reset(cpu_data, sipi_vector);
 935                         vcpu_reset();
 936                 }
 937                 iommu_check_pending_faults(cpu_data);
 938                 return;
 939         case VMEXIT_VMMCALL:
 940                 vcpu_handle_hypercall();
 941                 return;
 942         case VMEXIT_CR0_SEL_WRITE:
 943                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 944                 if (svm_handle_cr(cpu_data))
 945                         return;
 946                 break;
 947         case VMEXIT_MSR:
 948                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 949                 if (!vmcb->exitinfo1)
 950                         res = vcpu_handle_msr_read();
 951                 else
 952                         res = svm_handle_msr_write(cpu_data);
 953                 if (res)
 954                         return;
 955                 break;
 956         case VMEXIT_NPF:
 957                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
 958                      vmcb->exitinfo2 >= XAPIC_BASE &&
 959                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
 960                         /* APIC access in non-AVIC mode */
 961                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
 962                         if (svm_handle_apic_access(vmcb))
 963                                 return;
 964                 } else {
 965                         /* General MMIO (IOAPIC, PCI etc) */
 966                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
 967                         if (vcpu_handle_mmio_access())
 968                                 return;
 969                 }
 970
 971                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
 972                              "error code is %x\n", vmcb->exitinfo2,
 973                              vmcb->exitinfo1 & 0xf);
 974                 break;
 975         case VMEXIT_XSETBV:
 976                 if (vcpu_handle_xsetbv())
 977                         return;
 978                 break;
 979         case VMEXIT_IOIO:
 980                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
 981                 if (vcpu_handle_io_access())
 982                         return;
 983                 break;
 984         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
 985         default:
 986                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
 987                              "exitinfo1 %p exitinfo2 %p\n",
 988                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
 989         }
 990         dump_guest_regs(guest_regs, vmcb);
 991         panic_park();
 992 }
 993
 994 void vcpu_park(void)
 995 {
 996         svm_vcpu_reset(this_cpu_data(), APIC_BSP_PSEUDO_SIPI);
 997         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
 998         this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
 999
1000         vcpu_tlb_flush();
1001 }
1002
1003 void vcpu_nmi_handler(void)
1004 {
1005 }
1006
1007 void vcpu_tlb_flush(void)
1008 {
1009         struct vmcb *vmcb = &this_cpu_data()->vmcb;
1010
1011         if (has_flush_by_asid)
1012                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1013         else
1014                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1015 }
1016
1017 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1018                               unsigned long pc, unsigned int *size)
1019 {
1020         struct vmcb *vmcb = &this_cpu_data()->vmcb;
1021         unsigned long start;
1022
1023         if (has_assists) {
1024                 if (!*size)
1025                         return NULL;
1026                 start = vmcb->rip - pc;
1027                 if (start < vmcb->bytes_fetched) {
1028                         *size = vmcb->bytes_fetched - start;
1029                         return &vmcb->guest_bytes[start];
1030                 } else {
1031                         return NULL;
1032                 }
1033         } else {
1034                 return vcpu_map_inst(pg_structs, pc, size);
1035         }
1036 }
1037
1038 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1039                                     struct vcpu_io_bitmap *iobm)
1040 {
1041         iobm->data = cell->svm.iopm;
1042         iobm->size = sizeof(cell->svm.iopm);
1043 }
1044
1045 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1046 {
1047         struct vmcb *vmcb = &this_cpu_data()->vmcb;
1048
1049         x_state->efer = vmcb->efer;
1050         x_state->rflags = vmcb->rflags;
1051         x_state->cs = vmcb->cs.selector;
1052         x_state->rip = vmcb->rip;
1053 }
1054
1055 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1056 void enable_irq(void)
1057 {
1058         asm volatile("stgi; sti" : : : "memory");
1059 }
1060
1061 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1062 void disable_irq(void)
1063 {
1064         asm volatile("cli; clgi" : : : "memory");
1065 }