hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_CLEARED_BITS    ~X86_CR0_NW
  41
  42 #define MTRR_DEFTYPE            0x2ff
  43
  44 #define PAT_RESET_VALUE         0x0007040600070406UL
  45
  46 static bool has_avic, has_assists, has_flush_by_asid;
  47
  48 static const struct segment invalid_seg;
  49
  50 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  51
  52 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  53         [ SVM_MSRPM_0000 ] = {
  54                 [      0/4 ...  0x017/4 ] = 0,
  55                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  56                 [  0x01c/4 ...  0x2fb/4 ] = 0,
  57                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  58                 [  0x300/4 ...  0x7ff/4 ] = 0,
  59                 /* x2APIC MSRs - emulated if not present */
  60                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  61                 [  0x804/4 ...  0x807/4 ] = 0,
  62                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  63                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  64                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  65                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  66                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  67                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  68                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  69                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  70                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  71                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  72                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  73                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  74                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  75                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  76                 [  0x840/4 ... 0x1fff/4 ] = 0,
  77         },
  78         [ SVM_MSRPM_C000 ] = {
  79                 [      0/4 ...  0x07f/4 ] = 0,
  80                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  81                 [  0x084/4 ... 0x1fff/4 ] = 0
  82         },
  83         [ SVM_MSRPM_C001 ] = {
  84                 [      0/4 ... 0x1fff/4 ] = 0,
  85         },
  86         [ SVM_MSRPM_RESV ] = {
  87                 [      0/4 ... 0x1fff/4 ] = 0,
  88         }
  89 };
  90
  91 /* This page is mapped so the code begins at 0x000ffff0 */
  92 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  93         [0xff0] = 0xfa, /* 1: cli */
  94         [0xff1] = 0xf4, /*    hlt */
  95         [0xff2] = 0xeb,
  96         [0xff3] = 0xfc  /*    jmp 1b */
  97 };
  98
  99 static void *parked_mode_npt;
 100
 101 static void *avic_page;
 102
 103 static int svm_check_features(void)
 104 {
 105         /* SVM is available */
 106         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 107                 return -ENODEV;
 108
 109         /* Nested paging */
 110         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 111                 return -EIO;
 112
 113         /* Decode assists */
 114         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 115                 has_assists = true;
 116
 117         /* AVIC support */
 118         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 119                 has_avic = true;
 120
 121         /* TLB Flush by ASID support */
 122         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 123                 has_flush_by_asid = true;
 124
 125         return 0;
 126 }
 127
 128 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 129                                      const struct desc_table_reg *dtr)
 130 {
 131         struct svm_segment tmp = { 0 };
 132
 133         if (dtr) {
 134                 tmp.base = dtr->base;
 135                 tmp.limit = dtr->limit & 0xffff;
 136         }
 137
 138         *svm_segment = tmp;
 139 }
 140
 141 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
 142 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 143                                          const struct segment *segment)
 144 {
 145         u32 ar;
 146
 147         svm_segment->selector = segment->selector;
 148
 149         if (segment->access_rights == 0x10000) {
 150                 svm_segment->access_rights = 0;
 151         } else {
 152                 ar = segment->access_rights;
 153                 svm_segment->access_rights =
 154                         ((ar & 0xf000) >> 4) | (ar & 0x00ff);
 155         }
 156
 157         svm_segment->limit = segment->limit;
 158         svm_segment->base = segment->base;
 159 }
 160
 161 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 162 {
 163         /* No real need for this function; used for consistency with vmx.c */
 164         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 165         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 166
 167         return true;
 168 }
 169
 170 static int vmcb_setup(struct per_cpu *cpu_data)
 171 {
 172         struct vmcb *vmcb = &cpu_data->vmcb;
 173
 174         memset(vmcb, 0, sizeof(struct vmcb));
 175
 176         vmcb->cr0 = read_cr0() & SVM_CR0_CLEARED_BITS;
 177         vmcb->cr3 = cpu_data->linux_cr3;
 178         vmcb->cr4 = read_cr4();
 179
 180         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 181         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 182         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 183         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 184         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 185         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 186         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 187
 188         set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
 189         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 190         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 191
 192         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 193
 194         vmcb->rflags = 0x02;
 195         /* Indicate success to the caller of arch_entry */
 196         vmcb->rax = 0;
 197         vmcb->rsp = cpu_data->linux_sp +
 198                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 199         vmcb->rip = cpu_data->linux_ip;
 200
 201         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 202         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 203         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 204         vmcb->star = read_msr(MSR_STAR);
 205         vmcb->lstar = read_msr(MSR_LSTAR);
 206         vmcb->cstar = read_msr(MSR_CSTAR);
 207         vmcb->sfmask = read_msr(MSR_SFMASK);
 208         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 209
 210         vmcb->dr6 = 0x00000ff0;
 211         vmcb->dr7 = 0x00000400;
 212
 213         /* Make the hypervisor visible */
 214         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 215
 216         /* Linux uses custom PAT setting */
 217         vmcb->g_pat = read_msr(MSR_IA32_PAT);
 218
 219         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 220         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 221         /* TODO: Do we need this for SVM ? */
 222         /* vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID; */
 223         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 224         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 225         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 226
 227         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 228         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 229
 230         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 231
 232         vmcb->np_enable = 1;
 233         /* No more than one guest owns the CPU */
 234         vmcb->guest_asid = 1;
 235
 236         /* TODO: Setup AVIC */
 237
 238         /* Explicitly mark all of the state as new */
 239         vmcb->clean_bits = 0;
 240
 241         return svm_set_cell_config(cpu_data->cell, vmcb);
 242 }
 243
 244 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 245                                      unsigned long gphys,
 246                                      unsigned long flags)
 247 {
 248         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 249                         gphys, flags);
 250 }
 251
 252 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 253 {
 254         /* See APMv2, Section 15.25.5 */
 255         *pte = (next_pt & 0x000ffffffffff000UL) |
 256                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 257 }
 258
 259 int vcpu_vendor_init(void)
 260 {
 261         struct paging_structures parking_pt;
 262         unsigned long vm_cr;
 263         int err, n;
 264
 265         err = svm_check_features();
 266         if (err)
 267                 return err;
 268
 269         vm_cr = read_msr(MSR_VM_CR);
 270         if (vm_cr & VM_CR_SVMDIS)
 271                 /* SVM disabled in BIOS */
 272                 return -EPERM;
 273
 274         /* Nested paging is the same as the native one */
 275         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 276         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 277                 npt_paging[n].set_next_pt = npt_set_next_pt;
 278
 279         /* Map guest parking code (shared between cells and CPUs) */
 280         parking_pt.root_paging = npt_paging;
 281         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 282         if (!parked_mode_npt)
 283                 return -ENOMEM;
 284         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 285                             PAGE_SIZE, 0x000ff000,
 286                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 287                             PAGING_NON_COHERENT);
 288         if (err)
 289                 return err;
 290
 291         /* This is always false for AMD now (except in nested SVM);
 292            see Sect. 16.3.1 in APMv2 */
 293         if (using_x2apic) {
 294                 /* allow direct x2APIC access except for ICR writes */
 295                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 296                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 297                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 298         } else {
 299                 if (has_avic) {
 300                         avic_page = page_alloc(&remap_pool, 1);
 301                         if (!avic_page)
 302                                 return -ENOMEM;
 303                 }
 304         }
 305
 306         return vcpu_cell_init(&root_cell);
 307 }
 308
 309 int vcpu_vendor_cell_init(struct cell *cell)
 310 {
 311         u64 flags;
 312         int err;
 313
 314         /* allocate iopm (two 4-K pages + 3 bits) */
 315         cell->svm.iopm = page_alloc(&mem_pool, 3);
 316         if (!cell->svm.iopm)
 317                 return -ENOMEM;
 318
 319         /* build root NPT of cell */
 320         cell->svm.npt_structs.root_paging = npt_paging;
 321         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 322         if (!cell->svm.npt_structs.root_table)
 323                 return -ENOMEM;
 324
 325         if (!has_avic) {
 326                 /*
 327                  * Map xAPIC as is; reads are passed, writes are trapped.
 328                  */
 329                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 330                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 331                                     PAGE_SIZE, XAPIC_BASE,
 332                                     flags,
 333                                     PAGING_NON_COHERENT);
 334         } else {
 335                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 336                 err = paging_create(&cell->svm.npt_structs,
 337                                     paging_hvirt2phys(avic_page),
 338                                     PAGE_SIZE, XAPIC_BASE,
 339                                     flags,
 340                                     PAGING_NON_COHERENT);
 341         }
 342
 343         return err;
 344 }
 345
 346 int vcpu_map_memory_region(struct cell *cell,
 347                            const struct jailhouse_memory *mem)
 348 {
 349         u64 phys_start = mem->phys_start;
 350         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 351
 352         if (mem->flags & JAILHOUSE_MEM_READ)
 353                 flags |= PAGE_FLAG_PRESENT;
 354         if (mem->flags & JAILHOUSE_MEM_WRITE)
 355                 flags |= PAGE_FLAG_RW;
 356         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 357                 flags |= PAGE_FLAG_NOEXECUTE;
 358         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 359                 phys_start = paging_hvirt2phys(&cell->comm_page);
 360
 361         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 362                              mem->virt_start, flags, PAGING_NON_COHERENT);
 363 }
 364
 365 int vcpu_unmap_memory_region(struct cell *cell,
 366                              const struct jailhouse_memory *mem)
 367 {
 368         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 369                               mem->size, PAGING_NON_COHERENT);
 370 }
 371
 372 void vcpu_vendor_cell_exit(struct cell *cell)
 373 {
 374         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 375                        PAGING_NON_COHERENT);
 376         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 377 }
 378
 379 int vcpu_init(struct per_cpu *cpu_data)
 380 {
 381         unsigned long efer;
 382         int err;
 383
 384         err = svm_check_features();
 385         if (err)
 386                 return err;
 387
 388         efer = read_msr(MSR_EFER);
 389         if (efer & EFER_SVME)
 390                 return -EBUSY;
 391
 392         efer |= EFER_SVME;
 393         write_msr(MSR_EFER, efer);
 394
 395         cpu_data->svm_state = SVMON;
 396
 397         if (!vmcb_setup(cpu_data))
 398                 return -EIO;
 399
 400         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 401
 402         return 0;
 403 }
 404
 405 void vcpu_exit(struct per_cpu *cpu_data)
 406 {
 407         unsigned long efer;
 408
 409         if (cpu_data->svm_state == SVMOFF)
 410                 return;
 411
 412         cpu_data->svm_state = SVMOFF;
 413
 414         /* We are leaving - set the GIF */
 415         asm volatile ("stgi" : : : "memory");
 416
 417         efer = read_msr(MSR_EFER);
 418         efer &= ~EFER_SVME;
 419         write_msr(MSR_EFER, efer);
 420
 421         write_msr(MSR_VM_HSAVE_PA, 0);
 422 }
 423
 424 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 425 {
 426         unsigned long vmcb_pa, host_stack;
 427
 428         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 429         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 430
 431         /*
 432          * XXX: Jailhouse doesn't use PAT, so it is explicitly set to the
 433          * reset value. However, this value is later combined with vmcb->g_pat
 434          * (as per APMv2, Sect. 15.25.8) which may lead to subtle bugs as the
 435          * actual memory type might slightly differ from what Linux expects.
 436          */
 437         write_msr(MSR_IA32_PAT, PAT_RESET_VALUE);
 438
 439         /* We enter Linux at the point arch_entry would return to as well.
 440          * rax is cleared to signal success to the caller. */
 441         asm volatile(
 442                 "clgi\n\t"
 443                 "mov (%%rdi),%%r15\n\t"
 444                 "mov 0x8(%%rdi),%%r14\n\t"
 445                 "mov 0x10(%%rdi),%%r13\n\t"
 446                 "mov 0x18(%%rdi),%%r12\n\t"
 447                 "mov 0x20(%%rdi),%%rbx\n\t"
 448                 "mov 0x28(%%rdi),%%rbp\n\t"
 449                 "mov %0, %%rax\n\t"
 450                 "vmload %%rax\n\t"
 451                 "vmrun %%rax\n\t"
 452                 "vmsave %%rax\n\t"
 453                 /* Restore hypervisor stack */
 454                 "mov %2, %%rsp\n\t"
 455                 "jmp svm_vmexit"
 456                 : /* no output */
 457                 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
 458                 : "memory", "r15", "r14", "r13", "r12",
 459                   "rbx", "rbp", "rax", "cc");
 460         __builtin_unreachable();
 461 }
 462
 463 void __attribute__((noreturn))
 464 vcpu_deactivate_vmm(struct registers *guest_regs)
 465 {
 466         struct per_cpu *cpu_data = this_cpu_data();
 467         struct vmcb *vmcb = &cpu_data->vmcb;
 468         unsigned long *stack = (unsigned long *)vmcb->rsp;
 469         unsigned long linux_ip = vmcb->rip;
 470
 471         /* We are leaving - set the GIF */
 472         asm volatile ("stgi" : : : "memory");
 473
 474         /*
 475          * Restore the MSRs.
 476          *
 477          * XXX: One could argue this is better to be done in
 478          * arch_cpu_restore(), however, it would require changes
 479          * to cpu_data to store STAR and friends.
 480          */
 481         write_msr(MSR_STAR, vmcb->star);
 482         write_msr(MSR_LSTAR, vmcb->lstar);
 483         write_msr(MSR_CSTAR, vmcb->cstar);
 484         write_msr(MSR_SFMASK, vmcb->sfmask);
 485         write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
 486         write_msr(MSR_IA32_PAT, vmcb->g_pat);
 487
 488         cpu_data->linux_cr3 = vmcb->cr3;
 489
 490         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 491         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 492         cpu_data->linux_idtr.base = vmcb->idtr.base;
 493         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 494
 495         cpu_data->linux_cs.selector = vmcb->cs.selector;
 496
 497         cpu_data->linux_tss.selector = vmcb->tr.selector;
 498
 499         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 500         cpu_data->linux_fs.base = vmcb->fs.base;
 501         cpu_data->linux_gs.base = vmcb->gs.base;
 502
 503         cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
 504         cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
 505         cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
 506
 507         cpu_data->linux_ds.selector = vmcb->ds.selector;
 508         cpu_data->linux_es.selector = vmcb->es.selector;
 509         cpu_data->linux_fs.selector = vmcb->fs.selector;
 510         cpu_data->linux_gs.selector = vmcb->gs.selector;
 511
 512         arch_cpu_restore(cpu_data, 0);
 513
 514         stack--;
 515         *stack = linux_ip;
 516
 517         asm volatile (
 518                 "mov %%rbx,%%rsp\n\t"
 519                 "pop %%r15\n\t"
 520                 "pop %%r14\n\t"
 521                 "pop %%r13\n\t"
 522                 "pop %%r12\n\t"
 523                 "pop %%r11\n\t"
 524                 "pop %%r10\n\t"
 525                 "pop %%r9\n\t"
 526                 "pop %%r8\n\t"
 527                 "pop %%rdi\n\t"
 528                 "pop %%rsi\n\t"
 529                 "pop %%rbp\n\t"
 530                 "add $8,%%rsp\n\t"
 531                 "pop %%rbx\n\t"
 532                 "pop %%rdx\n\t"
 533                 "pop %%rcx\n\t"
 534                 "mov %%rax,%%rsp\n\t"
 535                 "xor %%rax,%%rax\n\t"
 536                 "ret"
 537                 : : "a" (stack), "b" (guest_regs));
 538         __builtin_unreachable();
 539 }
 540
 541 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 542 {
 543         struct vmcb *vmcb = &cpu_data->vmcb;
 544         unsigned long val;
 545         bool ok = true;
 546
 547         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 548         vmcb->cr3 = 0;
 549         vmcb->cr4 = 0;
 550
 551         vmcb->rflags = 0x02;
 552
 553         val = 0;
 554         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 555                 val = 0xfff0;
 556                 sipi_vector = 0xf0;
 557         }
 558         vmcb->rip = val;
 559         vmcb->rsp = 0;
 560
 561         vmcb->cs.selector = sipi_vector << 8;
 562         vmcb->cs.base = sipi_vector << 12;
 563         vmcb->cs.limit = 0xffff;
 564         vmcb->cs.access_rights = 0x009b;
 565
 566         vmcb->ds.selector = 0;
 567         vmcb->ds.base = 0;
 568         vmcb->ds.limit = 0xffff;
 569         vmcb->ds.access_rights = 0x0093;
 570
 571         vmcb->es.selector = 0;
 572         vmcb->es.base = 0;
 573         vmcb->es.limit = 0xffff;
 574         vmcb->es.access_rights = 0x0093;
 575
 576         vmcb->fs.selector = 0;
 577         vmcb->fs.base = 0;
 578         vmcb->fs.limit = 0xffff;
 579         vmcb->fs.access_rights = 0x0093;
 580
 581         vmcb->gs.selector = 0;
 582         vmcb->gs.base = 0;
 583         vmcb->gs.limit = 0xffff;
 584         vmcb->gs.access_rights = 0x0093;
 585
 586         vmcb->ss.selector = 0;
 587         vmcb->ss.base = 0;
 588         vmcb->ss.limit = 0xffff;
 589         vmcb->ss.access_rights = 0x0093;
 590
 591         vmcb->tr.selector = 0;
 592         vmcb->tr.base = 0;
 593         vmcb->tr.limit = 0xffff;
 594         vmcb->tr.access_rights = 0x008b;
 595
 596         vmcb->ldtr.selector = 0;
 597         vmcb->ldtr.base = 0;
 598         vmcb->ldtr.limit = 0xffff;
 599         vmcb->ldtr.access_rights = 0x0082;
 600
 601         vmcb->gdtr.selector = 0;
 602         vmcb->gdtr.base = 0;
 603         vmcb->gdtr.limit = 0xffff;
 604         vmcb->gdtr.access_rights = 0;
 605
 606         vmcb->idtr.selector = 0;
 607         vmcb->idtr.base = 0;
 608         vmcb->idtr.limit = 0xffff;
 609         vmcb->idtr.access_rights = 0;
 610
 611         vmcb->efer = EFER_SVME;
 612
 613         /* These MSRs are undefined on reset */
 614         vmcb->star = 0;
 615         vmcb->lstar = 0;
 616         vmcb->cstar = 0;
 617         vmcb->sfmask = 0;
 618         vmcb->sysenter_cs = 0;
 619         vmcb->sysenter_eip = 0;
 620         vmcb->sysenter_esp = 0;
 621         vmcb->kerngsbase = 0;
 622
 623         vmcb->g_pat = PAT_RESET_VALUE;
 624
 625         vmcb->dr7 = 0x00000400;
 626
 627         /* Almost all of the guest state changed */
 628         vmcb->clean_bits = 0;
 629
 630         ok &= svm_set_cell_config(cpu_data->cell, vmcb);
 631
 632         /* This is always false, but to be consistent with vmx.c... */
 633         if (!ok) {
 634                 panic_printk("FATAL: CPU reset failed\n");
 635                 panic_stop();
 636         }
 637 }
 638
 639 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 640 {
 641         struct per_cpu *cpu_data = this_cpu_data();
 642         struct vmcb *vmcb = &cpu_data->vmcb;
 643         vmcb->rip += inst_len;
 644 }
 645
 646 static void update_efer(struct per_cpu *cpu_data)
 647 {
 648         struct vmcb *vmcb = &cpu_data->vmcb;
 649         unsigned long efer = vmcb->efer;
 650
 651         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 652                 return;
 653
 654         efer |= EFER_LMA;
 655
 656         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 657         if ((vmcb->efer ^ efer) & EFER_LMA)
 658                 vcpu_tlb_flush();
 659
 660         vmcb->efer = efer;
 661         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 662 }
 663
 664 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 665 {
 666         struct per_cpu *cpu_data = this_cpu_data();
 667         struct vmcb *vmcb = &cpu_data->vmcb;
 668
 669         if (vmcb->efer & EFER_LMA) {
 670                 pg_structs->root_paging = x86_64_paging;
 671                 pg_structs->root_table_gphys =
 672                         vmcb->cr3 & 0x000ffffffffff000UL;
 673         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 674                    !(vmcb->cr4 & X86_CR4_PAE)) {
 675                 pg_structs->root_paging = i386_paging;
 676                 pg_structs->root_table_gphys =
 677                         vmcb->cr3 & 0xfffff000UL;
 678         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 679                 /*
 680                  * Can be in non-paged protected mode as well, but
 681                  * the translation mechanism will stay the same ayway.
 682                  */
 683                 pg_structs->root_paging = realmode_paging;
 684                 /*
 685                  * This will make paging_get_guest_pages map the page
 686                  * that also contains the bootstrap code and, thus, is
 687                  * always present in a cell.
 688                  */
 689                 pg_structs->root_table_gphys = 0xff000;
 690         } else {
 691                 printk("FATAL: Unsupported paging mode\n");
 692                 return false;
 693         }
 694         return true;
 695 }
 696
 697 struct parse_context {
 698         unsigned int remaining;
 699         unsigned int size;
 700         unsigned long cs_base;
 701         const u8 *inst;
 702 };
 703
 704 static bool ctx_advance(struct parse_context *ctx,
 705                         unsigned long *pc,
 706                         struct guest_paging_structures *pg_structs)
 707 {
 708         if (!ctx->size) {
 709                 ctx->size = ctx->remaining;
 710                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 711                                           &ctx->size);
 712                 if (!ctx->inst)
 713                         return false;
 714                 ctx->remaining -= ctx->size;
 715                 *pc += ctx->size;
 716         }
 717         return true;
 718 }
 719
 720 static bool x86_parse_mov_to_cr(struct per_cpu *cpu_data,
 721                                 unsigned long pc,
 722                                 unsigned char reg,
 723                                 unsigned long *gpr)
 724 {
 725         struct guest_paging_structures pg_structs;
 726         struct vmcb *vmcb = &cpu_data->vmcb;
 727         struct parse_context ctx = {};
 728         /* No prefixes are supported yet */
 729         u8 opcodes[] = {0x0f, 0x22}, modrm;
 730         bool ok = false;
 731         int n;
 732
 733         ctx.remaining = ARRAY_SIZE(opcodes);
 734         if (!vcpu_get_guest_paging_structs(&pg_structs))
 735                 goto out;
 736         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 737
 738         if (!ctx_advance(&ctx, &pc, &pg_structs))
 739                 goto out;
 740
 741         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
 742                 if (*(ctx.inst) != opcodes[n])
 743                         goto out;
 744                 if (!ctx_advance(&ctx, &pc, &pg_structs))
 745                         goto out;
 746         }
 747
 748         if (!ctx_advance(&ctx, &pc, &pg_structs))
 749                 goto out;
 750
 751         modrm = *(ctx.inst);
 752
 753         if (((modrm & 0x38) >> 3) != reg)
 754                 goto out;
 755
 756         if (gpr)
 757                 *gpr = (modrm & 0x7);
 758
 759         ok = true;
 760 out:
 761         return ok;
 762 }
 763
 764 /*
 765  * XXX: The only visible reason to have this function (vmx.c consistency
 766  * aside) is to prevent cells from setting invalid CD+NW combinations that
 767  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 768  * altogether?
 769  */
 770 static bool svm_handle_cr(struct registers *guest_regs,
 771                           struct per_cpu *cpu_data)
 772 {
 773         struct vmcb *vmcb = &cpu_data->vmcb;
 774         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 775         unsigned long reg = -1, val, bits;
 776         bool ok = true;
 777
 778         if (has_assists) {
 779                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 780                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 781                         ok = false;
 782                         goto out;
 783                 }
 784                 reg = vmcb->exitinfo1 & 0x07;
 785         } else {
 786                 if (!x86_parse_mov_to_cr(cpu_data, vmcb->rip, 0, &reg)) {
 787                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 788                         ok = false;
 789                         goto out;
 790                 }
 791         };
 792
 793         if (reg == 4)
 794                 val = vmcb->rsp;
 795         else
 796                 val = ((unsigned long *)guest_regs)[15 - reg];
 797
 798         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 799         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 800         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 801         if ((val ^ vmcb->cr0) & bits)
 802                 vcpu_tlb_flush();
 803         /* TODO: better check for #GP reasons */
 804         vmcb->cr0 = val & SVM_CR0_CLEARED_BITS;
 805         if (val & X86_CR0_PG)
 806                 update_efer(cpu_data);
 807         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 808
 809 out:
 810         return ok;
 811 }
 812
 813 static bool svm_handle_msr_read(struct registers *guest_regs,
 814                 struct per_cpu *cpu_data)
 815 {
 816         if (guest_regs->rcx >= MSR_X2APIC_BASE &&
 817             guest_regs->rcx <= MSR_X2APIC_END) {
 818                 vcpu_skip_emulated_instruction(X86_INST_LEN_RDMSR);
 819                 x2apic_handle_read(guest_regs);
 820                 return true;
 821         } else {
 822                 panic_printk("FATAL: Unhandled MSR read: %x\n",
 823                              guest_regs->rcx);
 824                 return false;
 825         }
 826 }
 827
 828 static bool svm_handle_msr_write(struct registers *guest_regs,
 829                 struct per_cpu *cpu_data)
 830 {
 831         struct vmcb *vmcb = &cpu_data->vmcb;
 832         unsigned long efer, val;
 833         bool result = true;
 834
 835         if (guest_regs->rcx >= MSR_X2APIC_BASE &&
 836             guest_regs->rcx <= MSR_X2APIC_END) {
 837                 result = x2apic_handle_write(guest_regs, cpu_data);
 838                 goto out;
 839         }
 840         if (guest_regs->rcx == MSR_EFER) {
 841                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 842                 efer = (guest_regs->rax & 0xffffffff) |
 843                         (guest_regs->rdx << 32) | EFER_SVME;
 844                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 845                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 846                         vcpu_tlb_flush();
 847                 vmcb->efer = efer;
 848                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 849                 goto out;
 850         }
 851         if (guest_regs->rcx == MTRR_DEFTYPE) {
 852                 val = (guest_regs->rax & 0xffffffff) | (guest_regs->rdx << 32);
 853                 /*
 854                  * Quick (and very incomplete) guest MTRRs emulation.
 855                  *
 856                  * For Linux, emulating MTRR Enable bit seems to be enough.
 857                  * If it is cleared, we set hPAT to all zeroes, effectively
 858                  * making all NPT-mapped memory UC (see APMv2, Sect. 15.25.8).
 859                  *
 860                  * Otherwise, default PAT value is restored. This can also
 861                  * make NPT-mapped memory's type different from what Linux
 862                  * expects, however.
 863                  */
 864                 if (val & 0x800)
 865                         write_msr(MSR_IA32_PAT, PAT_RESET_VALUE);
 866                 else
 867                         write_msr(MSR_IA32_PAT, 0);
 868                 goto out;
 869         }
 870
 871         result = false;
 872         panic_printk("FATAL: Unhandled MSR write: %x\n",
 873                      guest_regs->rcx);
 874 out:
 875         if (result)
 876                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 877         return result;
 878 }
 879
 880 /*
 881  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 882  * be treated separately in svm_handle_avic_access().
 883  */
 884 static bool svm_handle_apic_access(struct registers *guest_regs,
 885                                    struct per_cpu *cpu_data)
 886 {
 887         struct vmcb *vmcb = &cpu_data->vmcb;
 888         struct guest_paging_structures pg_structs;
 889         unsigned int inst_len, offset;
 890         bool is_write;
 891
 892         /* The caller is responsible for sanity checks */
 893         is_write = !!(vmcb->exitinfo1 & 0x2);
 894         offset = vmcb->exitinfo2 - XAPIC_BASE;
 895
 896         if (offset & 0x00f)
 897                 goto out_err;
 898
 899         if (!vcpu_get_guest_paging_structs(&pg_structs))
 900                 goto out_err;
 901
 902         inst_len = apic_mmio_access(guest_regs, cpu_data, vmcb->rip,
 903                                     &pg_structs, offset >> 4, is_write);
 904         if (!inst_len)
 905                 goto out_err;
 906
 907         vcpu_skip_emulated_instruction(inst_len);
 908         return true;
 909
 910 out_err:
 911         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 912                      offset, is_write);
 913         return false;
 914 }
 915
 916 static void dump_guest_regs(struct registers *guest_regs, struct vmcb *vmcb)
 917 {
 918         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 919                      vmcb->rsp, vmcb->rflags);
 920         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 921                      guest_regs->rbx, guest_regs->rcx);
 922         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 923                      guest_regs->rsi, guest_regs->rdi);
 924         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 925                      vmcb->cs.selector,
 926                      vmcb->cs.base,
 927                      vmcb->cs.access_rights,
 928                      (vmcb->efer & EFER_LMA));
 929         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 930                      vmcb->cr3, vmcb->cr4);
 931         panic_printk("EFER: %p\n", vmcb->efer);
 932 }
 933
 934 static void svm_get_vcpu_pf_intercept(struct per_cpu *cpu_data,
 935                                       struct vcpu_pf_intercept *out)
 936 {
 937         struct vmcb *vmcb = &cpu_data->vmcb;
 938
 939         out->phys_addr = vmcb->exitinfo2;
 940         out->is_write = !!(vmcb->exitinfo1 & 0x2);
 941 }
 942
 943 static void svm_get_vcpu_io_intercept(struct per_cpu *cpu_data,
 944                                       struct vcpu_io_intercept *out)
 945 {
 946         struct vmcb *vmcb = &cpu_data->vmcb;
 947         u64 exitinfo = vmcb->exitinfo1;
 948
 949         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 950         out->port = (exitinfo >> 16) & 0xFFFF;
 951         out->size = (exitinfo >> 4) & 0x7;
 952         out->in = !!(exitinfo & 0x1);
 953         out->inst_len = vmcb->exitinfo2 - vmcb->rip;
 954         out->rep_or_str = !!(exitinfo & 0x0c);
 955 }
 956
 957 void vcpu_handle_exit(struct registers *guest_regs, struct per_cpu *cpu_data)
 958 {
 959         struct vmcb *vmcb = &cpu_data->vmcb;
 960         struct vcpu_execution_state x_state;
 961         struct vcpu_pf_intercept pf;
 962         struct vcpu_io_intercept io;
 963         bool res = false;
 964         int sipi_vector;
 965
 966         /* Restore GS value expected by per_cpu data accessors */
 967         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 968
 969         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 970         /*
 971          * All guest state is marked unmodified; individual handlers must clear
 972          * the bits as needed.
 973          */
 974         vmcb->clean_bits = 0xffffffff;
 975
 976         switch (vmcb->exitcode) {
 977         case VMEXIT_INVALID:
 978                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 979                              vmcb->exitcode);
 980                 break;
 981         case VMEXIT_NMI:
 982                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 983                 /* Temporarily enable GIF to consume pending NMI */
 984                 asm volatile("stgi; clgi" : : : "memory");
 985                 sipi_vector = x86_handle_events(cpu_data);
 986                 if (sipi_vector >= 0) {
 987                         printk("CPU %d received SIPI, vector %x\n",
 988                                cpu_data->cpu_id, sipi_vector);
 989                         svm_vcpu_reset(cpu_data, sipi_vector);
 990                         memset(guest_regs, 0, sizeof(*guest_regs));
 991                 }
 992                 iommu_check_pending_faults(cpu_data);
 993                 return;
 994         case VMEXIT_CPUID:
 995                 /* FIXME: We are not intercepting CPUID now */
 996                 return;
 997         case VMEXIT_VMMCALL:
 998                 vcpu_vendor_get_execution_state(&x_state);
 999                 vcpu_handle_hypercall(guest_regs, &x_state);
1000                 return;
1001         case VMEXIT_CR0_SEL_WRITE:
1002                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
1003                 if (svm_handle_cr(guest_regs, cpu_data))
1004                         return;
1005                 break;
1006         case VMEXIT_MSR:
1007                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
1008                 if (!vmcb->exitinfo1)
1009                         res = svm_handle_msr_read(guest_regs, cpu_data);
1010                 else
1011                         res = svm_handle_msr_write(guest_regs, cpu_data);
1012                 if (res)
1013                         return;
1014                 break;
1015         case VMEXIT_NPF:
1016                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
1017                      vmcb->exitinfo2 >= XAPIC_BASE &&
1018                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
1019                         /* APIC access in non-AVIC mode */
1020                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
1021                         if (svm_handle_apic_access(guest_regs, cpu_data))
1022                                 return;
1023                 } else {
1024                         /* General MMIO (IOAPIC, PCI etc) */
1025                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
1026                         svm_get_vcpu_pf_intercept(cpu_data, &pf);
1027                         if (vcpu_handle_pt_violation(guest_regs, &pf))
1028                                 return;
1029                 }
1030
1031                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
1032                              "error code is %x\n", vmcb->exitinfo2,
1033                              vmcb->exitinfo1 & 0xf);
1034                 break;
1035         case VMEXIT_XSETBV:
1036                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XSETBV]++;
1037                 if ((guest_regs->rax & X86_XCR0_FP) &&
1038                     (guest_regs->rax & ~cpuid_eax(0x0d)) == 0 &&
1039                     guest_regs->rcx == 0 && guest_regs->rdx == 0) {
1040                         vcpu_skip_emulated_instruction(X86_INST_LEN_XSETBV);
1041                         asm volatile(
1042                                 "xsetbv"
1043                                 : /* no output */
1044                                 : "a" (guest_regs->rax), "c" (0), "d" (0));
1045                         return;
1046                 }
1047                 panic_printk("FATAL: Invalid xsetbv parameters: "
1048                              "xcr[%d] = %x:%x\n", guest_regs->rcx,
1049                              guest_regs->rdx, guest_regs->rax);
1050                 break;
1051         case VMEXIT_IOIO:
1052                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
1053                 svm_get_vcpu_io_intercept(cpu_data, &io);
1054                 if (vcpu_handle_io_access(guest_regs, &io))
1055                         return;
1056                 break;
1057         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
1058         default:
1059                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
1060                              "exitinfo1 %p exitinfo2 %p\n",
1061                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
1062         }
1063         dump_guest_regs(guest_regs, vmcb);
1064         panic_park();
1065 }
1066
1067 void vcpu_park(struct per_cpu *cpu_data)
1068 {
1069         struct vmcb *vmcb = &cpu_data->vmcb;
1070
1071         svm_vcpu_reset(cpu_data, APIC_BSP_PSEUDO_SIPI);
1072         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
1073         vmcb->n_cr3 = paging_hvirt2phys(parked_mode_npt);
1074
1075         vcpu_tlb_flush();
1076 }
1077
1078 void vcpu_nmi_handler(void)
1079 {
1080 }
1081
1082 void vcpu_tlb_flush(void)
1083 {
1084         struct per_cpu *cpu_data = this_cpu_data();
1085         struct vmcb *vmcb = &cpu_data->vmcb;
1086
1087         if (has_flush_by_asid)
1088                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1089         else
1090                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1091 }
1092
1093 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1094                               unsigned long pc, unsigned int *size)
1095 {
1096         struct per_cpu *cpu_data = this_cpu_data();
1097         struct vmcb *vmcb = &cpu_data->vmcb;
1098         unsigned long start;
1099
1100         if (has_assists) {
1101                 if (!*size)
1102                         return NULL;
1103                 start = vmcb->rip - pc;
1104                 if (start < vmcb->bytes_fetched) {
1105                         *size = vmcb->bytes_fetched - start;
1106                         return &vmcb->guest_bytes[start];
1107                 } else {
1108                         return NULL;
1109                 }
1110         } else {
1111                 return vcpu_map_inst(pg_structs, pc, size);
1112         }
1113 }
1114
1115 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1116                                     struct vcpu_io_bitmap *iobm)
1117 {
1118         iobm->data = cell->svm.iopm;
1119         iobm->size = sizeof(cell->svm.iopm);
1120 }
1121
1122 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1123 {
1124         struct per_cpu *cpu_data = this_cpu_data();
1125
1126         x_state->efer = cpu_data->vmcb.efer;
1127         x_state->rflags = cpu_data->vmcb.rflags;
1128         x_state->cs = cpu_data->vmcb.cs.selector;
1129         x_state->rip = cpu_data->vmcb.rip;
1130 }
1131
1132 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1133 void enable_irq(void)
1134 {
1135         asm volatile("stgi; sti" : : : "memory");
1136 }
1137
1138 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1139 void disable_irq(void)
1140 {
1141         asm volatile("cli; clgi" : : : "memory");
1142 }