2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2013
5 * Copyright (c) Valentine Sinitsyn, 2014
8 * Jan Kiszka <jan.kiszka@siemens.com>
9 * Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
11 * Based on vmx.c written by Jan Kiszka.
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <jailhouse/entry.h>
18 #include <jailhouse/cell-config.h>
19 #include <jailhouse/control.h>
20 #include <jailhouse/paging.h>
21 #include <jailhouse/printk.h>
22 #include <jailhouse/processor.h>
23 #include <jailhouse/string.h>
24 #include <jailhouse/utils.h>
27 #include <asm/control.h>
28 #include <asm/iommu.h>
29 #include <asm/paging.h>
30 #include <asm/percpu.h>
31 #include <asm/processor.h>
36 * NW bit is ignored by all modern processors, however some
37 * combinations of NW and CD bits are prohibited by SVM (see APMv2,
38 * Sect. 15.5). To handle this, we always keep the NW bit off.
40 #define SVM_CR0_ALLOWED_BITS (~X86_CR0_NW)
42 static bool has_avic, has_assists, has_flush_by_asid;
44 static const struct segment invalid_seg;
46 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
48 /* bit cleared: direct access allowed */
49 // TODO: convert to whitelist
50 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
51 [ SVM_MSRPM_0000 ] = {
52 [ 0/4 ... 0x017/4 ] = 0,
53 [ 0x018/4 ... 0x01b/4 ] = 0x80, /* 0x01b (w) */
54 [ 0x01c/4 ... 0x1ff/4 ] = 0,
55 [ 0x200/4 ... 0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
56 [ 0x274/4 ... 0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
57 [ 0x278/4 ... 0x2fb/4 ] = 0,
58 [ 0x2fc/4 ... 0x2ff/4 ] = 0x80, /* 0x2ff (w) */
59 [ 0x300/4 ... 0x7ff/4 ] = 0,
60 /* x2APIC MSRs - emulated if not present */
61 [ 0x800/4 ... 0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
62 [ 0x804/4 ... 0x807/4 ] = 0,
63 [ 0x808/4 ... 0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
64 [ 0x80c/4 ... 0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
65 [ 0x810/4 ... 0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
66 [ 0x814/4 ... 0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
67 [ 0x818/4 ... 0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
68 [ 0x81c/4 ... 0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
69 [ 0x820/4 ... 0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
70 [ 0x824/4 ... 0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
71 [ 0x828/4 ... 0x82b/4 ] = 0x03, /* 0x828 (rw) */
72 [ 0x82c/4 ... 0x82f/4 ] = 0xc0, /* 0x82f (rw) */
73 [ 0x830/4 ... 0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
74 [ 0x834/4 ... 0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
75 [ 0x838/4 ... 0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
76 [ 0x83c/4 ... 0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
77 [ 0x840/4 ... 0x1fff/4 ] = 0,
79 [ SVM_MSRPM_C000 ] = {
80 [ 0/4 ... 0x07f/4 ] = 0,
81 [ 0x080/4 ... 0x083/4 ] = 0x02, /* 0x080 (w) */
82 [ 0x084/4 ... 0x1fff/4 ] = 0
84 [ SVM_MSRPM_C001 ] = {
85 [ 0/4 ... 0x1fff/4 ] = 0,
87 [ SVM_MSRPM_RESV ] = {
88 [ 0/4 ... 0x1fff/4 ] = 0,
92 /* This page is mapped so the code begins at 0x000ffff0 */
93 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
94 [0xff0] = 0xfa, /* 1: cli */
95 [0xff1] = 0xf4, /* hlt */
97 [0xff3] = 0xfc /* jmp 1b */
100 static void *parked_mode_npt;
102 static void *avic_page;
104 static int svm_check_features(void)
106 /* SVM is available */
107 if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
108 return trace_error(-ENODEV);
111 if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
112 return trace_error(-EIO);
115 if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
119 if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
122 /* TLB Flush by ASID support */
123 if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
124 has_flush_by_asid = true;
129 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
130 const struct desc_table_reg *dtr)
132 struct svm_segment tmp = { 0 };
135 tmp.base = dtr->base;
136 tmp.limit = dtr->limit & 0xffff;
142 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
143 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
144 const struct segment *segment)
148 svm_segment->selector = segment->selector;
150 if (segment->access_rights == 0x10000) {
151 svm_segment->access_rights = 0;
153 ar = segment->access_rights;
154 svm_segment->access_rights =
155 ((ar & 0xf000) >> 4) | (ar & 0x00ff);
158 svm_segment->limit = segment->limit;
159 svm_segment->base = segment->base;
162 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
164 /* No real need for this function; used for consistency with vmx.c */
165 vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
166 vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
171 static int vmcb_setup(struct per_cpu *cpu_data)
173 struct vmcb *vmcb = &cpu_data->vmcb;
175 memset(vmcb, 0, sizeof(struct vmcb));
177 vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
178 vmcb->cr3 = cpu_data->linux_cr3;
179 vmcb->cr4 = cpu_data->linux_cr4;
181 set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
182 set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
183 set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
184 set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
185 set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
186 set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
187 set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
189 set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
190 set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
191 set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
193 vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
196 /* Indicate success to the caller of arch_entry */
198 vmcb->rsp = cpu_data->linux_sp +
199 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
200 vmcb->rip = cpu_data->linux_ip;
202 vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
203 vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
204 vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
205 vmcb->star = read_msr(MSR_STAR);
206 vmcb->lstar = read_msr(MSR_LSTAR);
207 vmcb->cstar = read_msr(MSR_CSTAR);
208 vmcb->sfmask = read_msr(MSR_SFMASK);
209 vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
211 vmcb->dr6 = 0x00000ff0;
212 vmcb->dr7 = 0x00000400;
214 /* Make the hypervisor visible */
215 vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
217 vmcb->g_pat = cpu_data->pat;
219 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
220 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
221 /* TODO: Do we need this for SVM ? */
222 /* vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID; */
223 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
224 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
225 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
227 vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
228 vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
230 vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
233 /* No more than one guest owns the CPU */
234 vmcb->guest_asid = 1;
236 /* TODO: Setup AVIC */
238 /* Explicitly mark all of the state as new */
239 vmcb->clean_bits = 0;
241 return svm_set_cell_config(cpu_data->cell, vmcb);
244 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
248 return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
252 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
254 /* See APMv2, Section 15.25.5 */
255 *pte = (next_pt & 0x000ffffffffff000UL) |
256 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
259 int vcpu_vendor_init(void)
261 struct paging_structures parking_pt;
265 err = svm_check_features();
269 vm_cr = read_msr(MSR_VM_CR);
270 if (vm_cr & VM_CR_SVMDIS)
271 /* SVM disabled in BIOS */
272 return trace_error(-EPERM);
274 /* Nested paging is the same as the native one */
275 memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
276 for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
277 npt_paging[n].set_next_pt = npt_set_next_pt;
279 /* Map guest parking code (shared between cells and CPUs) */
280 parking_pt.root_paging = npt_paging;
281 parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
282 if (!parked_mode_npt)
284 err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
285 PAGE_SIZE, 0x000ff000,
286 PAGE_READONLY_FLAGS | PAGE_FLAG_US,
287 PAGING_NON_COHERENT);
291 /* This is always false for AMD now (except in nested SVM);
292 see Sect. 16.3.1 in APMv2 */
294 /* allow direct x2APIC access except for ICR writes */
295 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
296 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
297 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
300 avic_page = page_alloc(&remap_pool, 1);
302 return trace_error(-ENOMEM);
306 return vcpu_cell_init(&root_cell);
309 int vcpu_vendor_cell_init(struct cell *cell)
314 /* allocate iopm (two 4-K pages + 3 bits) */
315 cell->svm.iopm = page_alloc(&mem_pool, 3);
319 /* build root NPT of cell */
320 cell->svm.npt_structs.root_paging = npt_paging;
321 cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
322 if (!cell->svm.npt_structs.root_table)
327 * Map xAPIC as is; reads are passed, writes are trapped.
329 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
330 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
331 PAGE_SIZE, XAPIC_BASE,
333 PAGING_NON_COHERENT);
335 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
336 err = paging_create(&cell->svm.npt_structs,
337 paging_hvirt2phys(avic_page),
338 PAGE_SIZE, XAPIC_BASE,
340 PAGING_NON_COHERENT);
346 int vcpu_map_memory_region(struct cell *cell,
347 const struct jailhouse_memory *mem)
349 u64 phys_start = mem->phys_start;
350 u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
352 if (mem->flags & JAILHOUSE_MEM_READ)
353 flags |= PAGE_FLAG_PRESENT;
354 if (mem->flags & JAILHOUSE_MEM_WRITE)
355 flags |= PAGE_FLAG_RW;
356 if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
357 flags |= PAGE_FLAG_NOEXECUTE;
358 if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
359 phys_start = paging_hvirt2phys(&cell->comm_page);
361 return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
362 mem->virt_start, flags, PAGING_NON_COHERENT);
365 int vcpu_unmap_memory_region(struct cell *cell,
366 const struct jailhouse_memory *mem)
368 return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
369 mem->size, PAGING_NON_COHERENT);
372 void vcpu_vendor_cell_exit(struct cell *cell)
374 paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
375 PAGING_NON_COHERENT);
376 page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
379 int vcpu_init(struct per_cpu *cpu_data)
384 err = svm_check_features();
388 efer = read_msr(MSR_EFER);
389 if (efer & EFER_SVME)
390 return trace_error(-EBUSY);
393 write_msr(MSR_EFER, efer);
395 cpu_data->svm_state = SVMON;
397 if (!vmcb_setup(cpu_data))
398 return trace_error(-EIO);
401 * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
402 * set the values of reserved bits to the values found during the
403 * previous CR0 read."
404 * But we want to avoid surprises with new features unknown to us but
405 * set by Linux. So check if any assumed revered bit was set and bail
407 * Note that the APM defines all reserved CR4 bits as must-be-zero.
409 if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
412 /* bring CR0 and CR4 into well-defined states */
413 write_cr0(X86_CR0_HOST_STATE);
414 write_cr4(X86_CR4_HOST_STATE);
416 write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
421 void vcpu_exit(struct per_cpu *cpu_data)
425 if (cpu_data->svm_state == SVMOFF)
428 cpu_data->svm_state = SVMOFF;
430 /* We are leaving - set the GIF */
431 asm volatile ("stgi" : : : "memory");
433 efer = read_msr(MSR_EFER);
435 write_msr(MSR_EFER, efer);
437 write_msr(MSR_VM_HSAVE_PA, 0);
440 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
442 unsigned long vmcb_pa, host_stack;
444 vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
445 host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
447 /* We enter Linux at the point arch_entry would return to as well.
448 * rax is cleared to signal success to the caller. */
451 "mov (%%rdi),%%r15\n\t"
452 "mov 0x8(%%rdi),%%r14\n\t"
453 "mov 0x10(%%rdi),%%r13\n\t"
454 "mov 0x18(%%rdi),%%r12\n\t"
455 "mov 0x20(%%rdi),%%rbx\n\t"
456 "mov 0x28(%%rdi),%%rbp\n\t"
461 /* Restore hypervisor stack */
465 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
466 : "memory", "r15", "r14", "r13", "r12",
467 "rbx", "rbp", "rax", "cc");
468 __builtin_unreachable();
471 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
473 struct per_cpu *cpu_data = this_cpu_data();
474 struct vmcb *vmcb = &cpu_data->vmcb;
475 unsigned long *stack = (unsigned long *)vmcb->rsp;
476 unsigned long linux_ip = vmcb->rip;
481 * XXX: One could argue this is better to be done in
482 * arch_cpu_restore(), however, it would require changes
483 * to cpu_data to store STAR and friends.
485 write_msr(MSR_STAR, vmcb->star);
486 write_msr(MSR_LSTAR, vmcb->lstar);
487 write_msr(MSR_CSTAR, vmcb->cstar);
488 write_msr(MSR_SFMASK, vmcb->sfmask);
489 write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
491 cpu_data->linux_cr0 = vmcb->cr0;
492 cpu_data->linux_cr3 = vmcb->cr3;
494 cpu_data->linux_gdtr.base = vmcb->gdtr.base;
495 cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
496 cpu_data->linux_idtr.base = vmcb->idtr.base;
497 cpu_data->linux_idtr.limit = vmcb->idtr.limit;
499 cpu_data->linux_cs.selector = vmcb->cs.selector;
501 cpu_data->linux_tss.selector = vmcb->tr.selector;
503 cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
504 cpu_data->linux_fs.base = vmcb->fs.base;
505 cpu_data->linux_gs.base = vmcb->gs.base;
507 cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
508 cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
509 cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
511 cpu_data->linux_ds.selector = vmcb->ds.selector;
512 cpu_data->linux_es.selector = vmcb->es.selector;
513 cpu_data->linux_fs.selector = vmcb->fs.selector;
514 cpu_data->linux_gs.selector = vmcb->gs.selector;
516 arch_cpu_restore(cpu_data, 0);
522 "mov %%rbx,%%rsp\n\t"
538 "mov %%rax,%%rsp\n\t"
539 "xor %%rax,%%rax\n\t"
541 : : "a" (stack), "b" (&cpu_data->guest_regs));
542 __builtin_unreachable();
545 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
547 struct vmcb *vmcb = &cpu_data->vmcb;
551 vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
558 if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
565 vmcb->cs.selector = sipi_vector << 8;
566 vmcb->cs.base = sipi_vector << 12;
567 vmcb->cs.limit = 0xffff;
568 vmcb->cs.access_rights = 0x009b;
570 vmcb->ds.selector = 0;
572 vmcb->ds.limit = 0xffff;
573 vmcb->ds.access_rights = 0x0093;
575 vmcb->es.selector = 0;
577 vmcb->es.limit = 0xffff;
578 vmcb->es.access_rights = 0x0093;
580 vmcb->fs.selector = 0;
582 vmcb->fs.limit = 0xffff;
583 vmcb->fs.access_rights = 0x0093;
585 vmcb->gs.selector = 0;
587 vmcb->gs.limit = 0xffff;
588 vmcb->gs.access_rights = 0x0093;
590 vmcb->ss.selector = 0;
592 vmcb->ss.limit = 0xffff;
593 vmcb->ss.access_rights = 0x0093;
595 vmcb->tr.selector = 0;
597 vmcb->tr.limit = 0xffff;
598 vmcb->tr.access_rights = 0x008b;
600 vmcb->ldtr.selector = 0;
602 vmcb->ldtr.limit = 0xffff;
603 vmcb->ldtr.access_rights = 0x0082;
605 vmcb->gdtr.selector = 0;
607 vmcb->gdtr.limit = 0xffff;
608 vmcb->gdtr.access_rights = 0;
610 vmcb->idtr.selector = 0;
612 vmcb->idtr.limit = 0xffff;
613 vmcb->idtr.access_rights = 0;
615 vmcb->efer = EFER_SVME;
617 /* These MSRs are undefined on reset */
622 vmcb->sysenter_cs = 0;
623 vmcb->sysenter_eip = 0;
624 vmcb->sysenter_esp = 0;
625 vmcb->kerngsbase = 0;
627 vmcb->dr7 = 0x00000400;
629 /* Almost all of the guest state changed */
630 vmcb->clean_bits = 0;
632 ok &= svm_set_cell_config(cpu_data->cell, vmcb);
634 /* This is always false, but to be consistent with vmx.c... */
636 panic_printk("FATAL: CPU reset failed\n");
641 void vcpu_skip_emulated_instruction(unsigned int inst_len)
643 struct per_cpu *cpu_data = this_cpu_data();
644 struct vmcb *vmcb = &cpu_data->vmcb;
645 vmcb->rip += inst_len;
648 static void update_efer(struct per_cpu *cpu_data)
650 struct vmcb *vmcb = &cpu_data->vmcb;
651 unsigned long efer = vmcb->efer;
653 if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
658 /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
659 if ((vmcb->efer ^ efer) & EFER_LMA)
663 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
666 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
668 struct per_cpu *cpu_data = this_cpu_data();
669 struct vmcb *vmcb = &cpu_data->vmcb;
671 if (vmcb->efer & EFER_LMA) {
672 pg_structs->root_paging = x86_64_paging;
673 pg_structs->root_table_gphys =
674 vmcb->cr3 & 0x000ffffffffff000UL;
675 } else if ((vmcb->cr0 & X86_CR0_PG) &&
676 !(vmcb->cr4 & X86_CR4_PAE)) {
677 pg_structs->root_paging = i386_paging;
678 pg_structs->root_table_gphys =
679 vmcb->cr3 & 0xfffff000UL;
680 } else if (!(vmcb->cr0 & X86_CR0_PG)) {
682 * Can be in non-paged protected mode as well, but
683 * the translation mechanism will stay the same ayway.
685 pg_structs->root_paging = realmode_paging;
687 * This will make paging_get_guest_pages map the page
688 * that also contains the bootstrap code and, thus, is
689 * always present in a cell.
691 pg_structs->root_table_gphys = 0xff000;
693 printk("FATAL: Unsupported paging mode\n");
699 void vcpu_vendor_set_guest_pat(unsigned long val)
701 struct vmcb *vmcb = &this_cpu_data()->vmcb;
704 vmcb->clean_bits &= ~CLEAN_BITS_NP;
707 struct parse_context {
708 unsigned int remaining;
710 unsigned long cs_base;
714 static bool ctx_advance(struct parse_context *ctx,
716 struct guest_paging_structures *pg_structs)
719 ctx->size = ctx->remaining;
720 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
724 ctx->remaining -= ctx->size;
730 static bool x86_parse_mov_to_cr(struct per_cpu *cpu_data,
735 struct guest_paging_structures pg_structs;
736 struct vmcb *vmcb = &cpu_data->vmcb;
737 struct parse_context ctx = {};
738 /* No prefixes are supported yet */
739 u8 opcodes[] = {0x0f, 0x22}, modrm;
743 ctx.remaining = ARRAY_SIZE(opcodes);
744 if (!vcpu_get_guest_paging_structs(&pg_structs))
746 ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
748 if (!ctx_advance(&ctx, &pc, &pg_structs))
751 for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
752 if (*(ctx.inst) != opcodes[n])
754 if (!ctx_advance(&ctx, &pc, &pg_structs))
758 if (!ctx_advance(&ctx, &pc, &pg_structs))
763 if (((modrm & 0x38) >> 3) != reg)
767 *gpr = (modrm & 0x7);
775 * XXX: The only visible reason to have this function (vmx.c consistency
776 * aside) is to prevent cells from setting invalid CD+NW combinations that
777 * result in no more than VMEXIT_INVALID. Maybe we can get along without it
780 static bool svm_handle_cr(union registers *guest_regs,
781 struct per_cpu *cpu_data)
783 struct vmcb *vmcb = &cpu_data->vmcb;
784 /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
785 unsigned long reg = -1, val, bits;
789 if (!(vmcb->exitinfo1 & (1UL << 63))) {
790 panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
794 reg = vmcb->exitinfo1 & 0x07;
796 if (!x86_parse_mov_to_cr(cpu_data, vmcb->rip, 0, ®)) {
797 panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
806 val = guest_regs->by_index[15 - reg];
808 vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
809 /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
810 bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
811 if ((val ^ vmcb->cr0) & bits)
813 /* TODO: better check for #GP reasons */
814 vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
815 if (val & X86_CR0_PG)
816 update_efer(cpu_data);
817 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
823 static bool svm_handle_msr_write(union registers *guest_regs,
824 struct per_cpu *cpu_data)
826 struct vmcb *vmcb = &cpu_data->vmcb;
829 if (guest_regs->rcx == MSR_EFER) {
830 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
831 efer = get_wrmsr_value(guest_regs) | EFER_SVME;
832 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
833 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
836 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
837 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
841 return vcpu_handle_msr_write(guest_regs);
845 * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
846 * be treated separately in svm_handle_avic_access().
848 static bool svm_handle_apic_access(struct per_cpu *cpu_data)
850 struct vmcb *vmcb = &cpu_data->vmcb;
851 struct guest_paging_structures pg_structs;
852 unsigned int inst_len, offset;
855 /* The caller is responsible for sanity checks */
856 is_write = !!(vmcb->exitinfo1 & 0x2);
857 offset = vmcb->exitinfo2 - XAPIC_BASE;
862 if (!vcpu_get_guest_paging_structs(&pg_structs))
865 inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
870 vcpu_skip_emulated_instruction(inst_len);
874 panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
879 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
881 panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
882 vmcb->rsp, vmcb->rflags);
883 panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
884 guest_regs->rbx, guest_regs->rcx);
885 panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
886 guest_regs->rsi, guest_regs->rdi);
887 panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
888 vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
889 !!(vmcb->efer & EFER_LMA));
890 panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
891 vmcb->cr3, vmcb->cr4);
892 panic_printk("EFER: %p\n", vmcb->efer);
895 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
897 struct vmcb *vmcb = &this_cpu_data()->vmcb;
898 u64 exitinfo = vmcb->exitinfo1;
900 /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
901 io->port = (exitinfo >> 16) & 0xFFFF;
902 io->size = (exitinfo >> 4) & 0x7;
903 io->in = !!(exitinfo & 0x1);
904 io->inst_len = vmcb->exitinfo2 - vmcb->rip;
905 io->rep_or_str = !!(exitinfo & 0x0c);
908 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
910 struct vmcb *vmcb = &this_cpu_data()->vmcb;
912 mmio->phys_addr = vmcb->exitinfo2;
913 mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
916 void vcpu_handle_exit(struct per_cpu *cpu_data)
918 union registers *guest_regs = &cpu_data->guest_regs;
919 struct vmcb *vmcb = &cpu_data->vmcb;
923 /* Restore GS value expected by per_cpu data accessors */
924 write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
926 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
928 * All guest state is marked unmodified; individual handlers must clear
929 * the bits as needed.
931 vmcb->clean_bits = 0xffffffff;
933 switch (vmcb->exitcode) {
935 panic_printk("FATAL: VM-Entry failure, error %d\n",
939 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
940 /* Temporarily enable GIF to consume pending NMI */
941 asm volatile("stgi; clgi" : : : "memory");
942 sipi_vector = x86_handle_events(cpu_data);
943 if (sipi_vector >= 0) {
944 printk("CPU %d received SIPI, vector %x\n",
945 cpu_data->cpu_id, sipi_vector);
946 svm_vcpu_reset(cpu_data, sipi_vector);
949 iommu_check_pending_faults(cpu_data);
952 /* FIXME: We are not intercepting CPUID now */
955 vcpu_handle_hypercall();
957 case VMEXIT_CR0_SEL_WRITE:
958 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
959 if (svm_handle_cr(guest_regs, cpu_data))
963 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
964 if (!vmcb->exitinfo1)
965 res = vcpu_handle_msr_read(guest_regs);
967 res = svm_handle_msr_write(guest_regs, cpu_data);
972 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
973 vmcb->exitinfo2 >= XAPIC_BASE &&
974 vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
975 /* APIC access in non-AVIC mode */
976 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
977 if (svm_handle_apic_access(cpu_data))
980 /* General MMIO (IOAPIC, PCI etc) */
981 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
982 if (vcpu_handle_mmio_access())
986 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
987 "error code is %x\n", vmcb->exitinfo2,
988 vmcb->exitinfo1 & 0xf);
991 if (vcpu_handle_xsetbv())
995 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
996 if (vcpu_handle_io_access())
999 /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
1001 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
1002 "exitinfo1 %p exitinfo2 %p\n",
1003 vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
1005 dump_guest_regs(guest_regs, vmcb);
1009 void vcpu_park(void)
1011 svm_vcpu_reset(this_cpu_data(), APIC_BSP_PSEUDO_SIPI);
1012 /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
1013 this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
1018 void vcpu_nmi_handler(void)
1022 void vcpu_tlb_flush(void)
1024 struct per_cpu *cpu_data = this_cpu_data();
1025 struct vmcb *vmcb = &cpu_data->vmcb;
1027 if (has_flush_by_asid)
1028 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1030 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1033 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1034 unsigned long pc, unsigned int *size)
1036 struct per_cpu *cpu_data = this_cpu_data();
1037 struct vmcb *vmcb = &cpu_data->vmcb;
1038 unsigned long start;
1043 start = vmcb->rip - pc;
1044 if (start < vmcb->bytes_fetched) {
1045 *size = vmcb->bytes_fetched - start;
1046 return &vmcb->guest_bytes[start];
1051 return vcpu_map_inst(pg_structs, pc, size);
1055 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1056 struct vcpu_io_bitmap *iobm)
1058 iobm->data = cell->svm.iopm;
1059 iobm->size = sizeof(cell->svm.iopm);
1062 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1064 struct per_cpu *cpu_data = this_cpu_data();
1066 x_state->efer = cpu_data->vmcb.efer;
1067 x_state->rflags = cpu_data->vmcb.rflags;
1068 x_state->cs = cpu_data->vmcb.cs.selector;
1069 x_state->rip = cpu_data->vmcb.rip;
1072 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1073 void enable_irq(void)
1075 asm volatile("stgi; sti" : : : "memory");
1078 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1079 void disable_irq(void)
1081 asm volatile("cli; clgi" : : : "memory");