hypervisor/pci.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2014
   5  *
   6  * Authors:
   7  *  Ivan Kolchin <ivan.kolchin@siemens.com>
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  */
  13
  14 #include <jailhouse/control.h>
  15 #include <jailhouse/mmio.h>
  16 #include <jailhouse/pci.h>
  17 #include <jailhouse/printk.h>
  18 #include <jailhouse/utils.h>
  19
  20 #define MSIX_VECTOR_CTRL_DWORD          3
  21
  22 #define for_each_configured_pci_device(dev, cell)                       \
  23         for ((dev) = (cell)->pci_devices;                               \
  24              (dev) - (cell)->pci_devices < (cell)->config->num_pci_devices; \
  25              (dev)++)
  26
  27 #define for_each_pci_cap(cap, dev, counter)                             \
  28         for ((cap) = jailhouse_cell_pci_caps((dev)->cell->config) +     \
  29                 (dev)->info->caps_start, (counter) = 0;                 \
  30              (counter) < (dev)->info->num_caps;                         \
  31              (cap)++, (counter)++)
  32
  33 /* entry for PCI config space whitelist (granting access) */
  34 struct pci_cfg_access {
  35         u32 reg_num; /* Register number (4-byte aligned) */
  36         u32 mask; /* Bit set: access allowed */
  37 };
  38
  39 /* --- Whilelists for writing to PCI config space registers --- */
  40 /* Type 1: Endpoints */
  41 static const struct pci_cfg_access endpoint_write_access[] = {
  42         { 0x04, 0xffffffff }, /* Command, Status */
  43         { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
  44         { 0x3c, 0x000000ff }, /* Int Line */
  45 };
  46 /* Type 2: Bridges */
  47 static const struct pci_cfg_access bridge_write_access[] = {
  48         { 0x04, 0xffffffff }, /* Command, Status */
  49         { 0x0c, 0xff00ffff }, /* BIST, Latency Timer, Cacheline */
  50         { 0x3c, 0xffff00ff }, /* Int Line, Bridge Control */
  51 };
  52
  53 static void *pci_space;
  54 static u64 mmcfg_start, mmcfg_end;
  55 static u8 end_bus;
  56
  57 static void *pci_get_device_mmcfg_base(u16 bdf)
  58 {
  59         return pci_space + ((unsigned long)bdf << 12);
  60 }
  61
  62 /**
  63  * Read from PCI config space.
  64  * @param bdf           16-bit bus/device/function ID of target.
  65  * @param address       Config space access address.
  66  * @param size          Access size (1, 2 or 4 bytes).
  67  *
  68  * @return Read value.
  69  *
  70  * @see pci_write_config
  71  */
  72 u32 pci_read_config(u16 bdf, u16 address, unsigned int size)
  73 {
  74         void *mmcfg_addr = pci_get_device_mmcfg_base(bdf) + address;
  75
  76         if (!pci_space || PCI_BUS(bdf) > end_bus)
  77                 return arch_pci_read_config(bdf, address, size);
  78
  79         if (size == 1)
  80                 return mmio_read8(mmcfg_addr);
  81         else if (size == 2)
  82                 return mmio_read16(mmcfg_addr);
  83         else
  84                 return mmio_read32(mmcfg_addr);
  85 }
  86
  87 /**
  88  * Write to PCI config space.
  89  * @param bdf           16-bit bus/device/function ID of target.
  90  * @param address       Config space access address.
  91  * @param value         Value to be written.
  92  * @param size          Access size (1, 2 or 4 bytes).
  93  *
  94  * @see pci_read_config
  95  */
  96 void pci_write_config(u16 bdf, u16 address, u32 value, unsigned int size)
  97 {
  98         void *mmcfg_addr = pci_get_device_mmcfg_base(bdf) + address;
  99
 100         if (!pci_space || PCI_BUS(bdf) > end_bus)
 101                 return arch_pci_write_config(bdf, address, value, size);
 102
 103         if (size == 1)
 104                 mmio_write8(mmcfg_addr, value);
 105         else if (size == 2)
 106                 mmio_write16(mmcfg_addr, value);
 107         else
 108                 mmio_write32(mmcfg_addr, value);
 109 }
 110
 111 /**
 112  * Look up device owned by a cell.
 113  * @param[in] cell      Owning cell.
 114  * @param bdf           16-bit bus/device/function ID.
 115  *
 116  * @return Pointer to owned PCI device or NULL.
 117  */
 118 struct pci_device *pci_get_assigned_device(const struct cell *cell, u16 bdf)
 119 {
 120         const struct jailhouse_pci_device *dev_info =
 121                 jailhouse_cell_pci_devices(cell->config);
 122         u32 n;
 123
 124         /* We iterate over the static device information to increase cache
 125          * locality. */
 126         for (n = 0; n < cell->config->num_pci_devices; n++)
 127                 if (dev_info[n].bdf == bdf)
 128                         return cell->pci_devices[n].cell ?
 129                                 &cell->pci_devices[n] : NULL;
 130
 131         return NULL;
 132 }
 133
 134 /**
 135  * Look up capability at given config space address.
 136  * @param device        The device to be accessed.
 137  * @param address       Config space access address.
 138  *
 139  * @return Corresponding capability structure or NULL if none found.
 140  *
 141  * @private
 142  */
 143 static const struct jailhouse_pci_capability *
 144 pci_find_capability(struct pci_device *device, u16 address)
 145 {
 146         const struct jailhouse_pci_capability *cap =
 147                 jailhouse_cell_pci_caps(device->cell->config) +
 148                 device->info->caps_start;
 149         u32 n;
 150
 151         for (n = 0; n < device->info->num_caps; n++, cap++)
 152                 if (cap->start <= address && cap->start + cap->len > address)
 153                         return cap;
 154
 155         return NULL;
 156 }
 157
 158 /**
 159  * Moderate config space read access.
 160  * @param device        The device to be accessed. If NULL, access will be
 161  *                      emulated, returning a value of -1.
 162  * @param address       Config space address.
 163  * @param size          Access size (1, 2 or 4 bytes).
 164  * @param value         Pointer to buffer to receive the emulated value if
 165  *                      PCI_ACCESS_DONE is returned.
 166  *
 167  * @return PCI_ACCESS_PERFORM or PCI_ACCESS_DONE.
 168  *
 169  * @see pci_cfg_write_moderate
 170  */
 171 enum pci_access pci_cfg_read_moderate(struct pci_device *device, u16 address,
 172                                       unsigned int size, u32 *value)
 173 {
 174         const struct jailhouse_pci_capability *cap;
 175         unsigned int cap_offs;
 176
 177         if (!device) {
 178                 *value = -1;
 179                 return PCI_ACCESS_DONE;
 180         }
 181
 182         if (device->info->type == JAILHOUSE_PCI_TYPE_IVSHMEM)
 183                 return pci_ivshmem_cfg_read(device, address, size, value);
 184
 185         if (address < PCI_CONFIG_HEADER_SIZE)
 186                 return PCI_ACCESS_PERFORM;
 187
 188         cap = pci_find_capability(device, address);
 189         if (!cap)
 190                 return PCI_ACCESS_PERFORM;
 191
 192         cap_offs = address - cap->start;
 193         if (cap->id == PCI_CAP_MSI && cap_offs >= 4 &&
 194             (cap_offs < 10 || (device->info->msi_64bits && cap_offs < 14))) {
 195                 *value = device->msi_registers.raw[cap_offs / 4] >>
 196                         ((cap_offs % 4) * 8);
 197                 return PCI_ACCESS_DONE;
 198         }
 199
 200         return PCI_ACCESS_PERFORM;
 201 }
 202
 203 static int pci_update_msix(struct pci_device *device,
 204                            const struct jailhouse_pci_capability *cap)
 205 {
 206         unsigned int n;
 207         int result;
 208
 209         for (n = 0; n < device->info->num_msix_vectors; n++) {
 210                 result = arch_pci_update_msix_vector(device, n);
 211                 if (result < 0)
 212                         return result;
 213         }
 214         return 0;
 215 }
 216
 217 /**
 218  * Moderate config space write access.
 219  * @param device        The device to be accessed. If NULL, access will be
 220  *                      rejected.
 221  * @param address       Config space address.
 222  * @param size          Access size (1, 2 or 4 bytes).
 223  * @param value         Value to be written.
 224  *
 225  * @return PCI_ACCESS_REJECT, PCI_ACCESS_PERFORM or PCI_ACCESS_DONE.
 226  *
 227  * @see pci_cfg_read_moderate
 228  */
 229 enum pci_access pci_cfg_write_moderate(struct pci_device *device, u16 address,
 230                                        unsigned int size, u32 value)
 231 {
 232         const struct jailhouse_pci_capability *cap;
 233         /* initialize list to work around wrong compiler warning */
 234         const struct pci_cfg_access *list = NULL;
 235         unsigned int bias_shift = (address % 4) * 8;
 236         u32 mask = BYTE_MASK(size) << bias_shift;
 237         unsigned int n, cap_offs, len = 0;
 238
 239         if (!device)
 240                 return PCI_ACCESS_REJECT;
 241
 242         if (device->info->type == JAILHOUSE_PCI_TYPE_IVSHMEM)
 243                 return pci_ivshmem_cfg_write(device, address, size, value);
 244
 245         if (address < PCI_CONFIG_HEADER_SIZE) {
 246                 if (device->info->type == JAILHOUSE_PCI_TYPE_DEVICE) {
 247                         list = endpoint_write_access;
 248                         len = ARRAY_SIZE(endpoint_write_access);
 249                 } else if (device->info->type == JAILHOUSE_PCI_TYPE_BRIDGE) {
 250                         list = bridge_write_access;
 251                         len = ARRAY_SIZE(bridge_write_access);
 252                 }
 253
 254                 for (n = 0; n < len; n++) {
 255                         if (list[n].reg_num == (address & 0xffc) &&
 256                             (list[n].mask & mask) == mask)
 257                                 return PCI_ACCESS_PERFORM;
 258                 }
 259
 260                 // HACK to allow PCI bus rescanning in root-cell
 261                 if (device->info->type == JAILHOUSE_PCI_TYPE_BRIDGE &&
 262                     device->cell == &root_cell)
 263                         return PCI_ACCESS_DONE;
 264
 265                 return PCI_ACCESS_REJECT;
 266         }
 267
 268         cap = pci_find_capability(device, address);
 269         if (!cap || !(cap->flags & JAILHOUSE_PCICAPS_WRITE))
 270                 return PCI_ACCESS_REJECT;
 271
 272         value <<= bias_shift;
 273
 274         cap_offs = address - cap->start;
 275         if (cap->id == PCI_CAP_MSI &&
 276             (cap_offs < 10 || (device->info->msi_64bits && cap_offs < 14))) {
 277                 device->msi_registers.raw[cap_offs / 4] &= ~mask;
 278                 device->msi_registers.raw[cap_offs / 4] |= value;
 279
 280                 if (arch_pci_update_msi(device, cap) < 0)
 281                         return PCI_ACCESS_REJECT;
 282
 283                 /*
 284                  * Address and data words are emulated, the control word is
 285                  * written as-is.
 286                  */
 287                 if (cap_offs >= 4)
 288                         return PCI_ACCESS_DONE;
 289         } else if (cap->id == PCI_CAP_MSIX && cap_offs < 4) {
 290                 device->msix_registers.raw &= ~mask;
 291                 device->msix_registers.raw |= value;
 292
 293                 if (pci_update_msix(device, cap) < 0)
 294                         return PCI_ACCESS_REJECT;
 295         }
 296
 297         return PCI_ACCESS_PERFORM;
 298 }
 299
 300 /**
 301  * Initialization of PCI subsystem.
 302  *
 303  * @return 0 on success, negative error code otherwise.
 304  */
 305 int pci_init(void)
 306 {
 307         unsigned int mmcfg_size;
 308         int err;
 309
 310         err = pci_cell_init(&root_cell);
 311         if (err)
 312                 return err;
 313
 314         mmcfg_start = system_config->platform_info.x86.mmconfig_base;
 315         if (mmcfg_start == 0)
 316                 return 0;
 317
 318         end_bus = system_config->platform_info.x86.mmconfig_end_bus;
 319         mmcfg_size = (end_bus + 1) * 256 * 4096;
 320         mmcfg_end = mmcfg_start + mmcfg_size - 4;
 321
 322         pci_space = page_alloc(&remap_pool, mmcfg_size / PAGE_SIZE);
 323         if (!pci_space)
 324                 return -ENOMEM;
 325
 326         return paging_create(&hv_paging_structs, mmcfg_start, mmcfg_size,
 327                              (unsigned long)pci_space,
 328                              PAGE_DEFAULT_FLAGS | PAGE_FLAG_UNCACHED,
 329                              PAGING_NON_COHERENT);
 330 }
 331
 332 static int pci_msix_access_handler(const struct cell *cell, bool is_write,
 333                                    u64 addr, u32 *value)
 334 {
 335         unsigned int dword = (addr % sizeof(union pci_msix_vector)) >> 2;
 336         struct pci_device *device = cell->msix_device_list;
 337         unsigned int index;
 338         u64 offs;
 339
 340         while (device) {
 341                 if (addr >= device->info->msix_address &&
 342                     addr < device->info->msix_address +
 343                            device->info->msix_region_size)
 344                         goto found;
 345                 device = device->next_msix_device;
 346         }
 347         return 0;
 348
 349 found:
 350         /* access must be DWORD-aligned */
 351         if (addr & 0x3)
 352                 goto invalid_access;
 353
 354         offs = addr - device->info->msix_address;
 355         index = offs / sizeof(union pci_msix_vector);
 356
 357         if (is_write) {
 358                 /*
 359                  * The PBA may share a page with the MSI-X table. Writing to
 360                  * PBA entries is undefined. We declare it as invalid.
 361                  */
 362                 if (index >= device->info->num_msix_vectors)
 363                         goto invalid_access;
 364                 if (dword == MSIX_VECTOR_CTRL_DWORD) {
 365                         mmio_write32(&device->msix_table[index].field.ctrl,
 366                                      *value);
 367                 } else {
 368                         device->msix_vectors[index].raw[dword] = *value;
 369                         if (arch_pci_update_msix_vector(device, index) < 0)
 370                                 goto invalid_access;
 371                 }
 372         } else {
 373                 if (index >= device->info->num_msix_vectors ||
 374                     dword == MSIX_VECTOR_CTRL_DWORD)
 375                         *value =
 376                             mmio_read32(((void *)device->msix_table) + offs);
 377                 else
 378                         *value = device->msix_vectors[index].raw[dword];
 379         }
 380         return 1;
 381
 382 invalid_access:
 383         panic_printk("FATAL: Invalid PCI MSIX BAR write, device "
 384                      "%02x:%02x.%x\n", PCI_BDF_PARAMS(device->info->bdf));
 385         return -1;
 386 }
 387
 388 /**
 389  * Handler for MMIO-accesses to PCI config space.
 390  * @param cell          Request issuing cell.
 391  * @param is_write      True if write access.
 392  * @param addr          Address accessed.
 393  * @param value         Pointer to value for reading/writing.
 394  *
 395  * @return 1 if handled successfully, 0 if unhandled, -1 on access error.
 396  */
 397 int pci_mmio_access_handler(const struct cell *cell, bool is_write,
 398                             u64 addr, u32 *value)
 399 {
 400         u32 mmcfg_offset, reg_addr;
 401         struct pci_device *device;
 402         enum pci_access access;
 403         int ret;
 404
 405         if (!pci_space || addr < mmcfg_start || addr > mmcfg_end) {
 406                 ret = pci_msix_access_handler(cell, is_write, addr, value);
 407                 if (ret == 0)
 408                         ret = ivshmem_mmio_access_handler(cell, is_write, addr,
 409                                                           value);
 410                 return ret;
 411         }
 412
 413         mmcfg_offset = addr - mmcfg_start;
 414         reg_addr = mmcfg_offset & 0xfff;
 415         /* access must be DWORD-aligned */
 416         if (reg_addr & 0x3)
 417                 goto invalid_access;
 418
 419         device = pci_get_assigned_device(cell, mmcfg_offset >> 12);
 420
 421         if (is_write) {
 422                 access = pci_cfg_write_moderate(device, reg_addr, 4, *value);
 423                 if (access == PCI_ACCESS_REJECT)
 424                         goto invalid_access;
 425                 if (access == PCI_ACCESS_PERFORM)
 426                         mmio_write32(pci_space + mmcfg_offset, *value);
 427         } else {
 428                 access = pci_cfg_read_moderate(device, reg_addr, 4, value);
 429                 if (access == PCI_ACCESS_PERFORM)
 430                         *value = mmio_read32(pci_space + mmcfg_offset);
 431         }
 432
 433         return 1;
 434
 435 invalid_access:
 436         panic_printk("FATAL: Invalid PCI MMCONFIG write, device %02x:%02x.%x, "
 437                      "reg: %\n", PCI_BDF_PARAMS(mmcfg_offset >> 12), reg_addr);
 438         return -1;
 439
 440 }
 441
 442 /**
 443  * Retrieve number of enabled MSI vector of a device.
 444  * @param device        The device to be examined.
 445  *
 446  * @return number of vectors.
 447  */
 448 unsigned int pci_enabled_msi_vectors(struct pci_device *device)
 449 {
 450         return device->msi_registers.msg32.enable ?
 451                 1 << device->msi_registers.msg32.mme : 0;
 452 }
 453
 454 static void pci_save_msi(struct pci_device *device,
 455                          const struct jailhouse_pci_capability *cap)
 456 {
 457         u16 bdf = device->info->bdf;
 458         unsigned int n;
 459
 460         for (n = 0; n < (device->info->msi_64bits ? 4 : 3); n++)
 461                 device->msi_registers.raw[n] =
 462                         pci_read_config(bdf, cap->start + n * 4, 4);
 463 }
 464
 465 static void pci_restore_msi(struct pci_device *device,
 466                             const struct jailhouse_pci_capability *cap)
 467 {
 468         unsigned int n;
 469
 470         for (n = 1; n < (device->info->msi_64bits ? 4 : 3); n++)
 471                 pci_write_config(device->info->bdf, cap->start + n * 4,
 472                                  device->msi_registers.raw[n], 4);
 473 }
 474
 475 static void pci_suppress_msix(struct pci_device *device,
 476                               const struct jailhouse_pci_capability *cap,
 477                               bool suppressed)
 478 {
 479         union pci_msix_registers regs = device->msix_registers;
 480
 481         if (suppressed)
 482                 regs.field.fmask = 1;
 483         pci_write_config(device->info->bdf, cap->start, regs.raw, 4);
 484 }
 485
 486 static void pci_save_msix(struct pci_device *device,
 487                           const struct jailhouse_pci_capability *cap)
 488 {
 489         unsigned int n, r;
 490
 491         device->msix_registers.raw =
 492                 pci_read_config(device->info->bdf, cap->start, 4);
 493
 494         for (n = 0; n < device->info->num_msix_vectors; n++)
 495                 for (r = 0; r < 3; r++)
 496                         device->msix_vectors[n].raw[r] =
 497                                 mmio_read32(&device->msix_table[n].raw[r]);
 498 }
 499
 500 static void pci_restore_msix(struct pci_device *device,
 501                              const struct jailhouse_pci_capability *cap)
 502 {
 503         unsigned int n, r;
 504
 505         for (n = 0; n < device->info->num_msix_vectors; n++)
 506                 for (r = 0; r < 3; r++)
 507                         mmio_write32(&device->msix_table[n].raw[r],
 508                                      device->msix_vectors[n].raw[r]);
 509         pci_suppress_msix(device, cap, false);
 510 }
 511
 512 /**
 513  * Prepare the handover of PCI devices to Jailhouse or back to Linux.
 514  */
 515 void pci_prepare_handover(void)
 516 {
 517         const struct jailhouse_pci_capability *cap;
 518         struct pci_device *device;
 519         unsigned int n;
 520
 521         if (!root_cell.pci_devices)
 522                 return;
 523
 524         for_each_configured_pci_device(device, &root_cell) {
 525                 if (device->cell)
 526                         for_each_pci_cap(cap, device, n)
 527                                 if (cap->id == PCI_CAP_MSI)
 528                                         arch_pci_suppress_msi(device, cap);
 529                                 else if (cap->id == PCI_CAP_MSIX)
 530                                         pci_suppress_msix(device, cap, true);
 531         }
 532 }
 533
 534 static int pci_add_virtual_device(struct cell *cell, struct pci_device *device)
 535 {
 536         device->cell = cell;
 537         device->next_virtual_device = cell->virtual_device_list;
 538         cell->virtual_device_list = device;
 539         return arch_pci_add_device(cell, device);
 540 }
 541
 542 static int pci_add_device(struct cell *cell, struct pci_device *device)
 543 {
 544         unsigned int size = device->info->msix_region_size;
 545         int err;
 546
 547         printk("Adding PCI device %02x:%02x.%x to cell \"%s\"\n",
 548                PCI_BDF_PARAMS(device->info->bdf), cell->config->name);
 549
 550         err = arch_pci_add_device(cell, device);
 551
 552         if (!err && device->info->msix_address) {
 553                 device->msix_table = page_alloc(&remap_pool, size / PAGE_SIZE);
 554                 if (!device->msix_table) {
 555                         err = -ENOMEM;
 556                         goto error_remove_dev;
 557                 }
 558
 559                 err = paging_create(&hv_paging_structs,
 560                                     device->info->msix_address, size,
 561                                     (unsigned long)device->msix_table,
 562                                     PAGE_DEFAULT_FLAGS | PAGE_FLAG_UNCACHED,
 563                                     PAGING_NON_COHERENT);
 564                 if (err)
 565                         goto error_page_free;
 566
 567                 device->next_msix_device = cell->msix_device_list;
 568                 cell->msix_device_list = device;
 569         }
 570         return 0;
 571
 572 error_page_free:
 573         page_free(&remap_pool, device->msix_table, size / PAGE_SIZE);
 574 error_remove_dev:
 575         arch_pci_remove_device(device);
 576         return err;
 577 }
 578
 579 static void pci_remove_virtual_device(struct pci_device *device)
 580 {
 581         struct pci_device *prev = device->cell->virtual_device_list;
 582
 583         arch_pci_remove_device(device);
 584         if (prev == device) {
 585                 device->cell->virtual_device_list = device->next_virtual_device;
 586         } else {
 587                 while (prev->next_virtual_device != device)
 588                         prev = prev->next_virtual_device;
 589                 prev->next_virtual_device = device->next_virtual_device;
 590         }
 591 }
 592
 593 static void pci_remove_device(struct pci_device *device)
 594 {
 595         unsigned int size = device->info->msix_region_size;
 596         struct pci_device *prev_msix_device;
 597
 598         printk("Removing PCI device %02x:%02x.%x from cell \"%s\"\n",
 599                PCI_BDF_PARAMS(device->info->bdf), device->cell->config->name);
 600         arch_pci_remove_device(device);
 601         pci_write_config(device->info->bdf, PCI_CFG_COMMAND,
 602                          PCI_CMD_INTX_OFF, 2);
 603
 604         if (!device->msix_table)
 605                 return;
 606
 607         /* cannot fail, destruction of same size as construction */
 608         paging_destroy(&hv_paging_structs, (unsigned long)device->msix_table,
 609                        size, PAGING_NON_COHERENT);
 610         page_free(&remap_pool, device->msix_table, size / PAGE_SIZE);
 611
 612         prev_msix_device = device->cell->msix_device_list;
 613         if (prev_msix_device == device) {
 614                 device->cell->msix_device_list = device->next_msix_device;
 615         } else {
 616                 while (prev_msix_device->next_msix_device != device)
 617                         prev_msix_device = prev_msix_device->next_msix_device;
 618                 prev_msix_device->next_msix_device = device->next_msix_device;
 619         }
 620 }
 621
 622 /**
 623  * Perform PCI-specific initialization for a new cell.
 624  * @param cell  Cell to be initialized.
 625  *
 626  * @return 0 on success, negative error code otherwise.
 627  *
 628  * @see pci_cell_exit
 629  */
 630 int pci_cell_init(struct cell *cell)
 631 {
 632         unsigned int devlist_pages = PAGES(cell->config->num_pci_devices *
 633                                            sizeof(struct pci_device));
 634         const struct jailhouse_pci_device *dev_infos =
 635                 jailhouse_cell_pci_devices(cell->config);
 636         const struct jailhouse_pci_capability *cap;
 637         struct pci_device *device, *root_device;
 638         unsigned int ndev, ncap;
 639         int err;
 640
 641         cell->pci_devices = page_alloc(&mem_pool, devlist_pages);
 642         if (!cell->pci_devices)
 643                 return -ENOMEM;
 644
 645         /*
 646          * We order device states in the same way as the static information
 647          * so that we can use the index of the latter to find the former. For
 648          * the other way around and for obtaining the owner cell, we use more
 649          * handy pointers. The cell pointer also encodes active ownership.
 650          */
 651         for (ndev = 0; ndev < cell->config->num_pci_devices; ndev++) {
 652                 if (dev_infos[ndev].num_msix_vectors > PCI_MAX_MSIX_VECTORS) {
 653                         err = -ERANGE;
 654                         goto error;
 655                 }
 656
 657                 device = &cell->pci_devices[ndev];
 658                 device->info = &dev_infos[ndev];
 659
 660                 if (device->info->type == JAILHOUSE_PCI_TYPE_IVSHMEM) {
 661                         err = pci_ivshmem_init(cell, device);
 662                         if (err)
 663                                 goto error;
 664                         err = pci_add_virtual_device(cell, device);
 665                         if (err)
 666                                 goto error;
 667                         continue;
 668                 }
 669
 670                 root_device = pci_get_assigned_device(&root_cell,
 671                                                       dev_infos[ndev].bdf);
 672                 if (root_device) {
 673                         pci_remove_device(root_device);
 674                         root_device->cell = NULL;
 675                 }
 676
 677                 err = pci_add_device(cell, device);
 678                 if (err)
 679                         goto error;
 680
 681                 device->cell = cell;
 682
 683                 for_each_pci_cap(cap, device, ncap)
 684                         if (cap->id == PCI_CAP_MSI)
 685                                 pci_save_msi(device, cap);
 686                         else if (cap->id == PCI_CAP_MSIX)
 687                                 pci_save_msix(device, cap);
 688         }
 689
 690         if (cell == &root_cell)
 691                 pci_prepare_handover();
 692
 693         return 0;
 694 error:
 695         pci_cell_exit(cell);
 696         return err;
 697 }
 698
 699 static void pci_return_device_to_root_cell(struct pci_device *device)
 700 {
 701         struct pci_device *root_device;
 702
 703         for_each_configured_pci_device(root_device, &root_cell)
 704                 if (root_device->info->domain == device->info->domain &&
 705                     root_device->info->bdf == device->info->bdf) {
 706                         if (pci_add_device(&root_cell, root_device) < 0)
 707                                 printk("WARNING: Failed to re-assign PCI "
 708                                        "device to root cell\n");
 709                         else
 710                                 root_device->cell = &root_cell;
 711                         break;
 712                 }
 713 }
 714
 715 /**
 716  * Perform PCI-specific cleanup for a cell under destruction.
 717  * @param cell  Cell to be destructed.
 718  *
 719  * @see pci_cell_init
 720  */
 721 void pci_cell_exit(struct cell *cell)
 722 {
 723         unsigned int devlist_pages = PAGES(cell->config->num_pci_devices *
 724                                            sizeof(struct pci_device));
 725         struct pci_device *device;
 726
 727         /*
 728          * Do not destroy the root cell. We will shut down the complete
 729          * hypervisor instead.
 730          */
 731         if (cell == &root_cell)
 732                 return;
 733
 734         for_each_configured_pci_device(device, cell)
 735                 if (device->cell) {
 736                         if (device->info->type == JAILHOUSE_PCI_TYPE_IVSHMEM) {
 737                                 pci_ivshmem_exit(device);
 738                                 pci_remove_virtual_device(device);
 739                         } else {
 740                                 pci_remove_device(device);
 741                                 pci_return_device_to_root_cell(device);
 742                         }
 743                 }
 744
 745         page_free(&mem_pool, cell->pci_devices, devlist_pages);
 746 }
 747
 748 /**
 749  * Apply PCI-specific configuration changes.
 750  * @param cell_added_removed    Cell that was added or removed to/from the
 751  *                              system or NULL.
 752  *
 753  * @see arch_config_commit
 754  */
 755 void pci_config_commit(struct cell *cell_added_removed)
 756 {
 757         const struct jailhouse_pci_capability *cap;
 758         struct pci_device *device;
 759         unsigned int n;
 760         int err = 0;
 761
 762         if (!cell_added_removed)
 763                 return;
 764
 765         for_each_configured_pci_device(device, &root_cell)
 766                 if (device->cell) {
 767                         for_each_pci_cap(cap, device, n) {
 768                                 if (cap->id == PCI_CAP_MSI) {
 769                                         err = arch_pci_update_msi(device, cap);
 770                                 } else if (cap->id == PCI_CAP_MSIX) {
 771                                         err = pci_update_msix(device, cap);
 772                                         pci_suppress_msix(device, cap, false);
 773                                 }
 774                                 if (err)
 775                                         goto error;
 776                         }
 777                         if (device->info->type == JAILHOUSE_PCI_TYPE_IVSHMEM) {
 778                                 err = pci_ivshmem_update_msix(device);
 779                                 if (err) {
 780                                         cap = NULL;
 781                                         goto error;
 782                                 }
 783                         }
 784                 }
 785         return;
 786
 787 error:
 788         panic_printk("FATAL: Unsupported MSI/MSI-X state, device %02x:%02x.%x",
 789                      PCI_BDF_PARAMS(device->info->bdf));
 790         if (cap)
 791                 panic_printk(", cap %d\n", cap->id);
 792         else
 793                 panic_printk("\n");
 794         panic_stop();
 795 }
 796
 797 /**
 798  * Shut down the PCI layer during hypervisor deactivation.
 799  */
 800 void pci_shutdown(void)
 801 {
 802         const struct jailhouse_pci_capability *cap;
 803         struct pci_device *device;
 804         unsigned int n;
 805
 806         if (!root_cell.pci_devices)
 807                 return;
 808
 809         for_each_configured_pci_device(device, &root_cell)
 810                 if (device->cell)
 811                         for_each_pci_cap(cap, device, n)
 812                                 if (cap->id == PCI_CAP_MSI)
 813                                         pci_restore_msi(device, cap);
 814                                 else if (cap->id == PCI_CAP_MSIX)
 815                                         pci_restore_msix(device, cap);
 816 }