2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2013
5 * Copyright (c) Valentine Sinitsyn, 2014
8 * Jan Kiszka <jan.kiszka@siemens.com>
9 * Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
11 * Based on vmx.c written by Jan Kiszka.
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <jailhouse/entry.h>
18 #include <jailhouse/cell.h>
19 #include <jailhouse/cell-config.h>
20 #include <jailhouse/control.h>
21 #include <jailhouse/paging.h>
22 #include <jailhouse/printk.h>
23 #include <jailhouse/processor.h>
24 #include <jailhouse/string.h>
25 #include <jailhouse/utils.h>
27 #include <asm/control.h>
28 #include <asm/iommu.h>
29 #include <asm/paging.h>
30 #include <asm/percpu.h>
31 #include <asm/processor.h>
36 * NW bit is ignored by all modern processors, however some
37 * combinations of NW and CD bits are prohibited by SVM (see APMv2,
38 * Sect. 15.5). To handle this, we always keep the NW bit off.
40 #define SVM_CR0_ALLOWED_BITS (~X86_CR0_NW)
42 static bool has_avic, has_assists, has_flush_by_asid;
44 static const struct segment invalid_seg;
46 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
48 /* bit cleared: direct access allowed */
49 // TODO: convert to whitelist
50 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
51 [ SVM_MSRPM_0000 ] = {
52 [ 0/4 ... 0x017/4 ] = 0,
53 [ 0x018/4 ... 0x01b/4 ] = 0x80, /* 0x01b (w) */
54 [ 0x01c/4 ... 0x1ff/4 ] = 0,
55 [ 0x200/4 ... 0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
56 [ 0x274/4 ... 0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
57 [ 0x278/4 ... 0x2fb/4 ] = 0,
58 [ 0x2fc/4 ... 0x2ff/4 ] = 0x80, /* 0x2ff (w) */
59 [ 0x300/4 ... 0x7ff/4 ] = 0,
60 /* x2APIC MSRs - emulated if not present */
61 [ 0x800/4 ... 0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
62 [ 0x804/4 ... 0x807/4 ] = 0,
63 [ 0x808/4 ... 0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
64 [ 0x80c/4 ... 0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
65 [ 0x810/4 ... 0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
66 [ 0x814/4 ... 0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
67 [ 0x818/4 ... 0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
68 [ 0x81c/4 ... 0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
69 [ 0x820/4 ... 0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
70 [ 0x824/4 ... 0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
71 [ 0x828/4 ... 0x82b/4 ] = 0x03, /* 0x828 (rw) */
72 [ 0x82c/4 ... 0x82f/4 ] = 0xc0, /* 0x82f (rw) */
73 [ 0x830/4 ... 0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
74 [ 0x834/4 ... 0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
75 [ 0x838/4 ... 0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
76 [ 0x83c/4 ... 0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
77 [ 0x840/4 ... 0x1fff/4 ] = 0,
79 [ SVM_MSRPM_C000 ] = {
80 [ 0/4 ... 0x07f/4 ] = 0,
81 [ 0x080/4 ... 0x083/4 ] = 0x02, /* 0x080 (w) */
82 [ 0x084/4 ... 0x1fff/4 ] = 0
84 [ SVM_MSRPM_C001 ] = {
85 [ 0/4 ... 0x1fff/4 ] = 0,
87 [ SVM_MSRPM_RESV ] = {
88 [ 0/4 ... 0x1fff/4 ] = 0,
92 /* This page is mapped so the code begins at 0x000ffff0 */
93 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
94 [0xff0] = 0xfa, /* 1: cli */
95 [0xff1] = 0xf4, /* hlt */
97 [0xff3] = 0xfc /* jmp 1b */
100 static void *parked_mode_npt;
102 static void *avic_page;
104 static int svm_check_features(void)
106 /* SVM is available */
107 if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
108 return trace_error(-ENODEV);
111 if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
112 return trace_error(-EIO);
115 if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
119 if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
122 /* TLB Flush by ASID support */
123 if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
124 has_flush_by_asid = true;
129 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
130 const struct desc_table_reg *dtr)
132 svm_segment->base = dtr->base;
133 svm_segment->limit = dtr->limit & 0xffff;
136 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
137 const struct segment *segment)
139 svm_segment->selector = segment->selector;
140 svm_segment->access_rights = ((segment->access_rights & 0xf000) >> 4) |
141 (segment->access_rights & 0x00ff);
142 svm_segment->limit = segment->limit;
143 svm_segment->base = segment->base;
146 static void svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
148 vmcb->iopm_base_pa = paging_hvirt2phys(cell->arch.svm.iopm);
149 vmcb->n_cr3 = paging_hvirt2phys(cell->arch.svm.npt_structs.root_table);
152 static void vmcb_setup(struct per_cpu *cpu_data)
154 struct vmcb *vmcb = &cpu_data->vmcb;
156 memset(vmcb, 0, sizeof(struct vmcb));
158 vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
159 vmcb->cr3 = cpu_data->linux_cr3;
160 vmcb->cr4 = cpu_data->linux_cr4;
162 set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
163 set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
164 set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
165 set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
166 set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
167 set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
168 set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
169 set_svm_segment_from_segment(&vmcb->ldtr, &invalid_seg);
171 set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
172 set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
174 vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
177 /* Indicate success to the caller of arch_entry */
179 vmcb->rsp = cpu_data->linux_sp +
180 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
181 vmcb->rip = cpu_data->linux_ip;
183 vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
184 vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
185 vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
186 vmcb->star = read_msr(MSR_STAR);
187 vmcb->lstar = read_msr(MSR_LSTAR);
188 vmcb->cstar = read_msr(MSR_CSTAR);
189 vmcb->sfmask = read_msr(MSR_SFMASK);
190 vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
192 vmcb->dr6 = 0x00000ff0;
193 vmcb->dr7 = 0x00000400;
195 /* Make the hypervisor visible */
196 vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
198 vmcb->g_pat = cpu_data->pat;
200 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
201 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
202 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID;
203 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
204 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
205 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
207 vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
208 vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
210 vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
213 /* No more than one guest owns the CPU */
214 vmcb->guest_asid = 1;
216 /* TODO: Setup AVIC */
218 /* Explicitly mark all of the state as new */
219 vmcb->clean_bits = 0;
221 svm_set_cell_config(cpu_data->cell, vmcb);
224 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
228 return paging_virt2phys(&cpu_data->cell->arch.svm.npt_structs,
232 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
234 /* See APMv2, Section 15.25.5 */
235 *pte = (next_pt & 0x000ffffffffff000UL) |
236 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
239 int vcpu_vendor_init(void)
241 struct paging_structures parking_pt;
245 err = svm_check_features();
249 vm_cr = read_msr(MSR_VM_CR);
250 if (vm_cr & VM_CR_SVMDIS)
251 /* SVM disabled in BIOS */
252 return trace_error(-EPERM);
254 /* Nested paging is the same as the native one */
255 memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
256 for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
257 npt_paging[n].set_next_pt = npt_set_next_pt;
259 /* Map guest parking code (shared between cells and CPUs) */
260 parking_pt.root_paging = npt_paging;
261 parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
262 if (!parked_mode_npt)
264 err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
265 PAGE_SIZE, 0x000ff000,
266 PAGE_READONLY_FLAGS | PAGE_FLAG_US,
267 PAGING_NON_COHERENT);
271 /* This is always false for AMD now (except in nested SVM);
272 see Sect. 16.3.1 in APMv2 */
274 /* allow direct x2APIC access except for ICR writes */
275 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
276 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
277 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
280 avic_page = page_alloc(&remap_pool, 1);
282 return trace_error(-ENOMEM);
286 return vcpu_cell_init(&root_cell);
289 int vcpu_vendor_cell_init(struct cell *cell)
294 /* allocate iopm (two 4-K pages + 3 bits) */
295 cell->arch.svm.iopm = page_alloc(&mem_pool, 3);
296 if (!cell->arch.svm.iopm)
299 /* build root NPT of cell */
300 cell->arch.svm.npt_structs.root_paging = npt_paging;
301 cell->arch.svm.npt_structs.root_table =
302 (page_table_t)cell->arch.root_table_page;
306 * Map xAPIC as is; reads are passed, writes are trapped.
308 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
309 err = paging_create(&cell->arch.svm.npt_structs, XAPIC_BASE,
310 PAGE_SIZE, XAPIC_BASE,
312 PAGING_NON_COHERENT);
314 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
315 err = paging_create(&cell->arch.svm.npt_structs,
316 paging_hvirt2phys(avic_page),
317 PAGE_SIZE, XAPIC_BASE,
319 PAGING_NON_COHERENT);
327 page_free(&mem_pool, cell->arch.svm.iopm, 3);
332 int vcpu_map_memory_region(struct cell *cell,
333 const struct jailhouse_memory *mem)
335 u64 phys_start = mem->phys_start;
336 u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
338 if (mem->flags & JAILHOUSE_MEM_READ)
339 flags |= PAGE_FLAG_PRESENT;
340 if (mem->flags & JAILHOUSE_MEM_WRITE)
341 flags |= PAGE_FLAG_RW;
342 if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
343 flags |= PAGE_FLAG_NOEXECUTE;
344 if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
345 phys_start = paging_hvirt2phys(&cell->comm_page);
347 return paging_create(&cell->arch.svm.npt_structs, phys_start, mem->size,
348 mem->virt_start, flags, PAGING_NON_COHERENT);
351 int vcpu_unmap_memory_region(struct cell *cell,
352 const struct jailhouse_memory *mem)
354 return paging_destroy(&cell->arch.svm.npt_structs, mem->virt_start,
355 mem->size, PAGING_NON_COHERENT);
358 void vcpu_vendor_cell_exit(struct cell *cell)
360 paging_destroy(&cell->arch.svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
361 PAGING_NON_COHERENT);
362 page_free(&mem_pool, cell->arch.svm.iopm, 3);
365 int vcpu_init(struct per_cpu *cpu_data)
370 err = svm_check_features();
374 efer = read_msr(MSR_EFER);
375 if (efer & EFER_SVME)
376 return trace_error(-EBUSY);
379 write_msr(MSR_EFER, efer);
381 cpu_data->svm_state = SVMON;
383 vmcb_setup(cpu_data);
386 * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
387 * set the values of reserved bits to the values found during the
388 * previous CR0 read."
389 * But we want to avoid surprises with new features unknown to us but
390 * set by Linux. So check if any assumed revered bit was set and bail
392 * Note that the APM defines all reserved CR4 bits as must-be-zero.
394 if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
397 /* bring CR0 and CR4 into well-defined states */
398 write_cr0(X86_CR0_HOST_STATE);
399 write_cr4(X86_CR4_HOST_STATE);
401 write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
406 void vcpu_exit(struct per_cpu *cpu_data)
410 if (cpu_data->svm_state == SVMOFF)
413 cpu_data->svm_state = SVMOFF;
415 /* We are leaving - set the GIF */
416 asm volatile ("stgi" : : : "memory");
418 efer = read_msr(MSR_EFER);
420 write_msr(MSR_EFER, efer);
422 write_msr(MSR_VM_HSAVE_PA, 0);
425 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
427 unsigned long vmcb_pa, host_stack;
429 vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
430 host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
432 /* We enter Linux at the point arch_entry would return to as well.
433 * rax is cleared to signal success to the caller. */
436 "mov (%%rdi),%%r15\n\t"
437 "mov 0x8(%%rdi),%%r14\n\t"
438 "mov 0x10(%%rdi),%%r13\n\t"
439 "mov 0x18(%%rdi),%%r12\n\t"
440 "mov 0x20(%%rdi),%%rbx\n\t"
441 "mov 0x28(%%rdi),%%rbp\n\t"
446 : "D" (cpu_data->linux_reg), "a" (vmcb_pa), "m" (host_stack));
447 __builtin_unreachable();
450 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
452 struct per_cpu *cpu_data = this_cpu_data();
453 struct vmcb *vmcb = &cpu_data->vmcb;
454 unsigned long *stack = (unsigned long *)vmcb->rsp;
455 unsigned long linux_ip = vmcb->rip;
457 cpu_data->linux_cr0 = vmcb->cr0;
458 cpu_data->linux_cr3 = vmcb->cr3;
460 cpu_data->linux_gdtr.base = vmcb->gdtr.base;
461 cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
462 cpu_data->linux_idtr.base = vmcb->idtr.base;
463 cpu_data->linux_idtr.limit = vmcb->idtr.limit;
465 cpu_data->linux_cs.selector = vmcb->cs.selector;
467 asm volatile("str %0" : "=m" (cpu_data->linux_tss.selector));
469 cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
470 cpu_data->linux_fs.base = read_msr(MSR_FS_BASE);
471 cpu_data->linux_gs.base = vmcb->gs.base;
473 cpu_data->linux_ds.selector = vmcb->ds.selector;
474 cpu_data->linux_es.selector = vmcb->es.selector;
476 asm volatile("mov %%fs,%0" : "=m" (cpu_data->linux_fs.selector));
477 asm volatile("mov %%gs,%0" : "=m" (cpu_data->linux_gs.selector));
479 arch_cpu_restore(cpu_data, 0);
485 "mov %%rbx,%%rsp\n\t"
501 "mov %%rax,%%rsp\n\t"
502 "xor %%rax,%%rax\n\t"
504 : : "a" (stack), "b" (&cpu_data->guest_regs));
505 __builtin_unreachable();
508 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
510 static const struct svm_segment dataseg_reset_state = {
514 .access_rights = 0x0093,
516 static const struct svm_segment dtr_reset_state = {
522 struct vmcb *vmcb = &cpu_data->vmcb;
525 vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
532 if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
539 vmcb->cs.selector = sipi_vector << 8;
540 vmcb->cs.base = sipi_vector << 12;
541 vmcb->cs.limit = 0xffff;
542 vmcb->cs.access_rights = 0x009b;
544 vmcb->ds = dataseg_reset_state;
545 vmcb->es = dataseg_reset_state;
546 vmcb->fs = dataseg_reset_state;
547 vmcb->gs = dataseg_reset_state;
548 vmcb->ss = dataseg_reset_state;
550 vmcb->tr.selector = 0;
552 vmcb->tr.limit = 0xffff;
553 vmcb->tr.access_rights = 0x008b;
555 vmcb->ldtr.selector = 0;
557 vmcb->ldtr.limit = 0xffff;
558 vmcb->ldtr.access_rights = 0x0082;
560 vmcb->gdtr = dtr_reset_state;
561 vmcb->idtr = dtr_reset_state;
563 vmcb->efer = EFER_SVME;
565 /* These MSRs are undefined on reset */
570 vmcb->sysenter_cs = 0;
571 vmcb->sysenter_eip = 0;
572 vmcb->sysenter_esp = 0;
573 vmcb->kerngsbase = 0;
575 vmcb->dr7 = 0x00000400;
577 /* Almost all of the guest state changed */
578 vmcb->clean_bits = 0;
580 svm_set_cell_config(cpu_data->cell, vmcb);
584 : : "a" (paging_hvirt2phys(vmcb)) : "memory");
585 /* vmload overwrites GS_BASE - restore the host state */
586 write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
589 void vcpu_skip_emulated_instruction(unsigned int inst_len)
591 this_cpu_data()->vmcb.rip += inst_len;
594 static void update_efer(struct vmcb *vmcb)
596 unsigned long efer = vmcb->efer;
598 if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
603 /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
604 if ((vmcb->efer ^ efer) & EFER_LMA)
608 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
611 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
613 struct vmcb *vmcb = &this_cpu_data()->vmcb;
615 if (vmcb->efer & EFER_LMA) {
616 pg_structs->root_paging = x86_64_paging;
617 pg_structs->root_table_gphys =
618 vmcb->cr3 & 0x000ffffffffff000UL;
619 } else if ((vmcb->cr0 & X86_CR0_PG) &&
620 !(vmcb->cr4 & X86_CR4_PAE)) {
621 pg_structs->root_paging = i386_paging;
622 pg_structs->root_table_gphys =
623 vmcb->cr3 & 0xfffff000UL;
624 } else if (!(vmcb->cr0 & X86_CR0_PG)) {
626 * Can be in non-paged protected mode as well, but
627 * the translation mechanism will stay the same ayway.
629 pg_structs->root_paging = realmode_paging;
631 * This will make paging_get_guest_pages map the page
632 * that also contains the bootstrap code and, thus, is
633 * always present in a cell.
635 pg_structs->root_table_gphys = 0xff000;
637 printk("FATAL: Unsupported paging mode\n");
643 void vcpu_vendor_set_guest_pat(unsigned long val)
645 struct vmcb *vmcb = &this_cpu_data()->vmcb;
648 vmcb->clean_bits &= ~CLEAN_BITS_NP;
651 struct parse_context {
652 unsigned int remaining;
654 unsigned long cs_base;
658 static bool ctx_advance(struct parse_context *ctx,
660 struct guest_paging_structures *pg_structs)
663 ctx->size = ctx->remaining;
664 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
668 ctx->remaining -= ctx->size;
674 static bool svm_parse_mov_to_cr(struct vmcb *vmcb, unsigned long pc,
675 unsigned char reg, unsigned long *gpr)
677 struct guest_paging_structures pg_structs;
678 struct parse_context ctx = {};
679 /* No prefixes are supported yet */
680 u8 opcodes[] = {0x0f, 0x22}, modrm;
683 ctx.remaining = ARRAY_SIZE(opcodes);
684 if (!vcpu_get_guest_paging_structs(&pg_structs))
686 ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
688 if (!ctx_advance(&ctx, &pc, &pg_structs))
691 for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++)
692 if (*(ctx.inst) != opcodes[n] ||
693 !ctx_advance(&ctx, &pc, &pg_structs))
696 if (!ctx_advance(&ctx, &pc, &pg_structs))
701 if (((modrm & 0x38) >> 3) != reg)
705 *gpr = (modrm & 0x7);
711 * XXX: The only visible reason to have this function (vmx.c consistency
712 * aside) is to prevent cells from setting invalid CD+NW combinations that
713 * result in no more than VMEXIT_INVALID. Maybe we can get along without it
716 static bool svm_handle_cr(struct per_cpu *cpu_data)
718 struct vmcb *vmcb = &cpu_data->vmcb;
719 /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
720 unsigned long reg = -1, val, bits;
723 if (!(vmcb->exitinfo1 & (1UL << 63))) {
724 panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
727 reg = vmcb->exitinfo1 & 0x07;
729 if (!svm_parse_mov_to_cr(vmcb, vmcb->rip, 0, ®)) {
730 panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
738 val = cpu_data->guest_regs.by_index[15 - reg];
740 vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
741 /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
742 bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
743 if ((val ^ vmcb->cr0) & bits)
745 /* TODO: better check for #GP reasons */
746 vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
747 if (val & X86_CR0_PG)
749 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
754 static bool svm_handle_msr_write(struct per_cpu *cpu_data)
756 struct vmcb *vmcb = &cpu_data->vmcb;
759 if (cpu_data->guest_regs.rcx == MSR_EFER) {
760 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
761 efer = get_wrmsr_value(&cpu_data->guest_regs) | EFER_SVME;
762 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
763 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
766 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
767 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
771 return vcpu_handle_msr_write();
775 * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
776 * be treated separately in svm_handle_avic_access().
778 static bool svm_handle_apic_access(struct vmcb *vmcb)
780 struct guest_paging_structures pg_structs;
781 unsigned int inst_len, offset;
784 /* The caller is responsible for sanity checks */
785 is_write = !!(vmcb->exitinfo1 & 0x2);
786 offset = vmcb->exitinfo2 - XAPIC_BASE;
791 if (!vcpu_get_guest_paging_structs(&pg_structs))
794 inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
799 vcpu_skip_emulated_instruction(inst_len);
803 panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
808 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
810 panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
811 vmcb->rsp, vmcb->rflags);
812 panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
813 guest_regs->rbx, guest_regs->rcx);
814 panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
815 guest_regs->rsi, guest_regs->rdi);
816 panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
817 vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
818 !!(vmcb->efer & EFER_LMA));
819 panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
820 vmcb->cr3, vmcb->cr4);
821 panic_printk("EFER: %p\n", vmcb->efer);
824 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
826 struct vmcb *vmcb = &this_cpu_data()->vmcb;
827 u64 exitinfo = vmcb->exitinfo1;
829 /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
830 io->port = (exitinfo >> 16) & 0xFFFF;
831 io->size = (exitinfo >> 4) & 0x7;
832 io->in = !!(exitinfo & 0x1);
833 io->inst_len = vmcb->exitinfo2 - vmcb->rip;
834 io->rep_or_str = !!(exitinfo & 0x0c);
837 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
839 struct vmcb *vmcb = &this_cpu_data()->vmcb;
841 mmio->phys_addr = vmcb->exitinfo2;
842 mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
845 void vcpu_handle_exit(struct per_cpu *cpu_data)
847 struct vmcb *vmcb = &cpu_data->vmcb;
851 vmcb->gs.base = read_msr(MSR_GS_BASE);
853 /* Restore GS value expected by per_cpu data accessors */
854 write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
856 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
858 * All guest state is marked unmodified; individual handlers must clear
859 * the bits as needed.
861 vmcb->clean_bits = 0xffffffff;
863 switch (vmcb->exitcode) {
865 panic_printk("FATAL: VM-Entry failure, error %d\n",
869 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
870 /* Temporarily enable GIF to consume pending NMI */
871 asm volatile("stgi; clgi" : : : "memory");
872 sipi_vector = x86_handle_events(cpu_data);
873 if (sipi_vector >= 0) {
874 printk("CPU %d received SIPI, vector %x\n",
875 cpu_data->cpu_id, sipi_vector);
876 svm_vcpu_reset(cpu_data, sipi_vector);
877 vcpu_reset(sipi_vector == APIC_BSP_PSEUDO_SIPI);
879 iommu_check_pending_faults();
882 vcpu_handle_hypercall();
884 case VMEXIT_CR0_SEL_WRITE:
885 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
886 if (svm_handle_cr(cpu_data))
893 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
894 if (!vmcb->exitinfo1)
895 res = vcpu_handle_msr_read();
897 res = svm_handle_msr_write(cpu_data);
902 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
903 vmcb->exitinfo2 >= XAPIC_BASE &&
904 vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
905 /* APIC access in non-AVIC mode */
906 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
907 if (svm_handle_apic_access(vmcb))
910 /* General MMIO (IOAPIC, PCI etc) */
911 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
912 if (vcpu_handle_mmio_access())
916 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
917 "error code is %x\n", vmcb->exitinfo2,
918 vmcb->exitinfo1 & 0xf);
921 if (vcpu_handle_xsetbv())
925 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
926 if (vcpu_handle_io_access())
929 /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
931 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
932 "exitinfo1 %p exitinfo2 %p\n",
933 vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
935 dump_guest_regs(&cpu_data->guest_regs, vmcb);
939 write_msr(MSR_GS_BASE, vmcb->gs.base);
944 svm_vcpu_reset(this_cpu_data(), APIC_BSP_PSEUDO_SIPI);
945 /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
946 this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
951 void vcpu_nmi_handler(void)
955 void vcpu_tlb_flush(void)
957 struct vmcb *vmcb = &this_cpu_data()->vmcb;
959 if (has_flush_by_asid)
960 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
962 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
965 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
966 unsigned long pc, unsigned int *size)
968 struct vmcb *vmcb = &this_cpu_data()->vmcb;
974 start = vmcb->rip - pc;
975 if (start < vmcb->bytes_fetched) {
976 *size = vmcb->bytes_fetched - start;
977 return &vmcb->guest_bytes[start];
982 return vcpu_map_inst(pg_structs, pc, size);
986 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
987 struct vcpu_io_bitmap *iobm)
989 iobm->data = cell->arch.svm.iopm;
990 iobm->size = sizeof(cell->arch.svm.iopm);
993 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
995 struct vmcb *vmcb = &this_cpu_data()->vmcb;
997 x_state->efer = vmcb->efer;
998 x_state->rflags = vmcb->rflags;
999 x_state->cs = vmcb->cs.selector;
1000 x_state->rip = vmcb->rip;
1003 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1004 void enable_irq(void)
1006 asm volatile("stgi; sti" : : : "memory");
1009 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1010 void disable_irq(void)
1012 asm volatile("cli; clgi" : : : "memory");