2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2013
5 * Copyright (c) Valentine Sinitsyn, 2014
8 * Jan Kiszka <jan.kiszka@siemens.com>
9 * Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
11 * Based on vmx.c written by Jan Kiszka.
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <jailhouse/entry.h>
18 #include <jailhouse/cell-config.h>
19 #include <jailhouse/control.h>
20 #include <jailhouse/paging.h>
21 #include <jailhouse/printk.h>
22 #include <jailhouse/processor.h>
23 #include <jailhouse/string.h>
24 #include <jailhouse/utils.h>
27 #include <asm/control.h>
28 #include <asm/iommu.h>
29 #include <asm/paging.h>
30 #include <asm/percpu.h>
31 #include <asm/processor.h>
36 * NW bit is ignored by all modern processors, however some
37 * combinations of NW and CD bits are prohibited by SVM (see APMv2,
38 * Sect. 15.5). To handle this, we always keep the NW bit off.
40 #define SVM_CR0_ALLOWED_BITS (~X86_CR0_NW)
42 #define MTRR_DEFTYPE 0x2ff
44 static bool has_avic, has_assists, has_flush_by_asid;
46 static const struct segment invalid_seg;
48 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
50 /* bit cleared: direct access allowed */
51 // TODO: convert to whitelist
52 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
53 [ SVM_MSRPM_0000 ] = {
54 [ 0/4 ... 0x017/4 ] = 0,
55 [ 0x018/4 ... 0x01b/4 ] = 0x80, /* 0x01b (w) */
56 [ 0x01c/4 ... 0x273/4 ] = 0,
57 [ 0x274/4 ... 0x277/4 ] = 0xc0, /* 0x277 (rw) */
58 [ 0x278/4 ... 0x2fb/4 ] = 0,
59 [ 0x2fc/4 ... 0x2ff/4 ] = 0x80, /* 0x2ff (w) */
60 [ 0x300/4 ... 0x7ff/4 ] = 0,
61 /* x2APIC MSRs - emulated if not present */
62 [ 0x800/4 ... 0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
63 [ 0x804/4 ... 0x807/4 ] = 0,
64 [ 0x808/4 ... 0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
65 [ 0x80c/4 ... 0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
66 [ 0x810/4 ... 0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
67 [ 0x814/4 ... 0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
68 [ 0x818/4 ... 0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
69 [ 0x81c/4 ... 0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
70 [ 0x820/4 ... 0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
71 [ 0x824/4 ... 0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
72 [ 0x828/4 ... 0x82b/4 ] = 0x03, /* 0x828 (rw) */
73 [ 0x82c/4 ... 0x82f/4 ] = 0xc0, /* 0x82f (rw) */
74 [ 0x830/4 ... 0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
75 [ 0x834/4 ... 0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
76 [ 0x838/4 ... 0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
77 [ 0x83c/4 ... 0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
78 [ 0x840/4 ... 0x1fff/4 ] = 0,
80 [ SVM_MSRPM_C000 ] = {
81 [ 0/4 ... 0x07f/4 ] = 0,
82 [ 0x080/4 ... 0x083/4 ] = 0x02, /* 0x080 (w) */
83 [ 0x084/4 ... 0x1fff/4 ] = 0
85 [ SVM_MSRPM_C001 ] = {
86 [ 0/4 ... 0x1fff/4 ] = 0,
88 [ SVM_MSRPM_RESV ] = {
89 [ 0/4 ... 0x1fff/4 ] = 0,
93 /* This page is mapped so the code begins at 0x000ffff0 */
94 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
95 [0xff0] = 0xfa, /* 1: cli */
96 [0xff1] = 0xf4, /* hlt */
98 [0xff3] = 0xfc /* jmp 1b */
101 static void *parked_mode_npt;
103 static void *avic_page;
105 static int svm_check_features(void)
107 /* SVM is available */
108 if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
109 return trace_error(-ENODEV);
112 if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
113 return trace_error(-EIO);
116 if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
120 if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
123 /* TLB Flush by ASID support */
124 if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
125 has_flush_by_asid = true;
130 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
131 const struct desc_table_reg *dtr)
133 struct svm_segment tmp = { 0 };
136 tmp.base = dtr->base;
137 tmp.limit = dtr->limit & 0xffff;
143 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
144 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
145 const struct segment *segment)
149 svm_segment->selector = segment->selector;
151 if (segment->access_rights == 0x10000) {
152 svm_segment->access_rights = 0;
154 ar = segment->access_rights;
155 svm_segment->access_rights =
156 ((ar & 0xf000) >> 4) | (ar & 0x00ff);
159 svm_segment->limit = segment->limit;
160 svm_segment->base = segment->base;
163 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
165 /* No real need for this function; used for consistency with vmx.c */
166 vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
167 vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
172 static int vmcb_setup(struct per_cpu *cpu_data)
174 struct vmcb *vmcb = &cpu_data->vmcb;
176 memset(vmcb, 0, sizeof(struct vmcb));
178 vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
179 vmcb->cr3 = cpu_data->linux_cr3;
180 vmcb->cr4 = cpu_data->linux_cr4;
182 set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
183 set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
184 set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
185 set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
186 set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
187 set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
188 set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
190 set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
191 set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
192 set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
194 vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
197 /* Indicate success to the caller of arch_entry */
199 vmcb->rsp = cpu_data->linux_sp +
200 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
201 vmcb->rip = cpu_data->linux_ip;
203 vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
204 vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
205 vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
206 vmcb->star = read_msr(MSR_STAR);
207 vmcb->lstar = read_msr(MSR_LSTAR);
208 vmcb->cstar = read_msr(MSR_CSTAR);
209 vmcb->sfmask = read_msr(MSR_SFMASK);
210 vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
212 vmcb->dr6 = 0x00000ff0;
213 vmcb->dr7 = 0x00000400;
215 /* Make the hypervisor visible */
216 vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
218 /* Linux uses custom PAT setting */
219 vmcb->g_pat = cpu_data->linux_pat;
221 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
222 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
223 /* TODO: Do we need this for SVM ? */
224 /* vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID; */
225 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
226 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
227 vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
229 vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
230 vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
232 vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
235 /* No more than one guest owns the CPU */
236 vmcb->guest_asid = 1;
238 /* TODO: Setup AVIC */
240 /* Explicitly mark all of the state as new */
241 vmcb->clean_bits = 0;
243 return svm_set_cell_config(cpu_data->cell, vmcb);
246 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
250 return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
254 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
256 /* See APMv2, Section 15.25.5 */
257 *pte = (next_pt & 0x000ffffffffff000UL) |
258 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
261 int vcpu_vendor_init(void)
263 struct paging_structures parking_pt;
267 err = svm_check_features();
271 vm_cr = read_msr(MSR_VM_CR);
272 if (vm_cr & VM_CR_SVMDIS)
273 /* SVM disabled in BIOS */
274 return trace_error(-EPERM);
276 /* Nested paging is the same as the native one */
277 memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
278 for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
279 npt_paging[n].set_next_pt = npt_set_next_pt;
281 /* Map guest parking code (shared between cells and CPUs) */
282 parking_pt.root_paging = npt_paging;
283 parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
284 if (!parked_mode_npt)
286 err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
287 PAGE_SIZE, 0x000ff000,
288 PAGE_READONLY_FLAGS | PAGE_FLAG_US,
289 PAGING_NON_COHERENT);
293 /* This is always false for AMD now (except in nested SVM);
294 see Sect. 16.3.1 in APMv2 */
296 /* allow direct x2APIC access except for ICR writes */
297 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
298 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
299 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
302 avic_page = page_alloc(&remap_pool, 1);
304 return trace_error(-ENOMEM);
308 return vcpu_cell_init(&root_cell);
311 int vcpu_vendor_cell_init(struct cell *cell)
316 /* allocate iopm (two 4-K pages + 3 bits) */
317 cell->svm.iopm = page_alloc(&mem_pool, 3);
321 /* build root NPT of cell */
322 cell->svm.npt_structs.root_paging = npt_paging;
323 cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
324 if (!cell->svm.npt_structs.root_table)
329 * Map xAPIC as is; reads are passed, writes are trapped.
331 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
332 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
333 PAGE_SIZE, XAPIC_BASE,
335 PAGING_NON_COHERENT);
337 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
338 err = paging_create(&cell->svm.npt_structs,
339 paging_hvirt2phys(avic_page),
340 PAGE_SIZE, XAPIC_BASE,
342 PAGING_NON_COHERENT);
348 int vcpu_map_memory_region(struct cell *cell,
349 const struct jailhouse_memory *mem)
351 u64 phys_start = mem->phys_start;
352 u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
354 if (mem->flags & JAILHOUSE_MEM_READ)
355 flags |= PAGE_FLAG_PRESENT;
356 if (mem->flags & JAILHOUSE_MEM_WRITE)
357 flags |= PAGE_FLAG_RW;
358 if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
359 flags |= PAGE_FLAG_NOEXECUTE;
360 if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
361 phys_start = paging_hvirt2phys(&cell->comm_page);
363 return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
364 mem->virt_start, flags, PAGING_NON_COHERENT);
367 int vcpu_unmap_memory_region(struct cell *cell,
368 const struct jailhouse_memory *mem)
370 return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
371 mem->size, PAGING_NON_COHERENT);
374 void vcpu_vendor_cell_exit(struct cell *cell)
376 paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
377 PAGING_NON_COHERENT);
378 page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
381 int vcpu_init(struct per_cpu *cpu_data)
386 err = svm_check_features();
390 efer = read_msr(MSR_EFER);
391 if (efer & EFER_SVME)
392 return trace_error(-EBUSY);
395 write_msr(MSR_EFER, efer);
397 cpu_data->svm_state = SVMON;
399 if (!vmcb_setup(cpu_data))
400 return trace_error(-EIO);
403 * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
404 * set the values of reserved bits to the values found during the
405 * previous CR0 read."
406 * But we want to avoid surprises with new features unknown to us but
407 * set by Linux. So check if any assumed revered bit was set and bail
409 * Note that the APM defines all reserved CR4 bits as must-be-zero.
411 if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
414 /* bring CR0 and CR4 into well-defined states */
415 write_cr0(X86_CR0_HOST_STATE);
416 write_cr4(X86_CR4_HOST_STATE);
418 write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
423 void vcpu_exit(struct per_cpu *cpu_data)
427 if (cpu_data->svm_state == SVMOFF)
430 cpu_data->svm_state = SVMOFF;
432 /* We are leaving - set the GIF */
433 asm volatile ("stgi" : : : "memory");
435 efer = read_msr(MSR_EFER);
437 write_msr(MSR_EFER, efer);
439 write_msr(MSR_VM_HSAVE_PA, 0);
442 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
444 unsigned long vmcb_pa, host_stack;
446 vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
447 host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
449 /* We enter Linux at the point arch_entry would return to as well.
450 * rax is cleared to signal success to the caller. */
453 "mov (%%rdi),%%r15\n\t"
454 "mov 0x8(%%rdi),%%r14\n\t"
455 "mov 0x10(%%rdi),%%r13\n\t"
456 "mov 0x18(%%rdi),%%r12\n\t"
457 "mov 0x20(%%rdi),%%rbx\n\t"
458 "mov 0x28(%%rdi),%%rbp\n\t"
463 /* Restore hypervisor stack */
467 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
468 : "memory", "r15", "r14", "r13", "r12",
469 "rbx", "rbp", "rax", "cc");
470 __builtin_unreachable();
473 void __attribute__((noreturn))
474 vcpu_deactivate_vmm(struct registers *guest_regs)
476 struct per_cpu *cpu_data = this_cpu_data();
477 struct vmcb *vmcb = &cpu_data->vmcb;
478 unsigned long *stack = (unsigned long *)vmcb->rsp;
479 unsigned long linux_ip = vmcb->rip;
484 * XXX: One could argue this is better to be done in
485 * arch_cpu_restore(), however, it would require changes
486 * to cpu_data to store STAR and friends.
488 write_msr(MSR_STAR, vmcb->star);
489 write_msr(MSR_LSTAR, vmcb->lstar);
490 write_msr(MSR_CSTAR, vmcb->cstar);
491 write_msr(MSR_SFMASK, vmcb->sfmask);
492 write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
494 cpu_data->linux_cr0 = vmcb->cr0;
495 cpu_data->linux_cr3 = vmcb->cr3;
497 cpu_data->linux_gdtr.base = vmcb->gdtr.base;
498 cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
499 cpu_data->linux_idtr.base = vmcb->idtr.base;
500 cpu_data->linux_idtr.limit = vmcb->idtr.limit;
502 cpu_data->linux_cs.selector = vmcb->cs.selector;
504 cpu_data->linux_tss.selector = vmcb->tr.selector;
506 cpu_data->linux_pat = vmcb->g_pat;
507 cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
508 cpu_data->linux_fs.base = vmcb->fs.base;
509 cpu_data->linux_gs.base = vmcb->gs.base;
511 cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
512 cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
513 cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
515 cpu_data->linux_ds.selector = vmcb->ds.selector;
516 cpu_data->linux_es.selector = vmcb->es.selector;
517 cpu_data->linux_fs.selector = vmcb->fs.selector;
518 cpu_data->linux_gs.selector = vmcb->gs.selector;
520 arch_cpu_restore(cpu_data, 0);
526 "mov %%rbx,%%rsp\n\t"
542 "mov %%rax,%%rsp\n\t"
543 "xor %%rax,%%rax\n\t"
545 : : "a" (stack), "b" (guest_regs));
546 __builtin_unreachable();
549 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
551 struct vmcb *vmcb = &cpu_data->vmcb;
555 vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
562 if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
569 vmcb->cs.selector = sipi_vector << 8;
570 vmcb->cs.base = sipi_vector << 12;
571 vmcb->cs.limit = 0xffff;
572 vmcb->cs.access_rights = 0x009b;
574 vmcb->ds.selector = 0;
576 vmcb->ds.limit = 0xffff;
577 vmcb->ds.access_rights = 0x0093;
579 vmcb->es.selector = 0;
581 vmcb->es.limit = 0xffff;
582 vmcb->es.access_rights = 0x0093;
584 vmcb->fs.selector = 0;
586 vmcb->fs.limit = 0xffff;
587 vmcb->fs.access_rights = 0x0093;
589 vmcb->gs.selector = 0;
591 vmcb->gs.limit = 0xffff;
592 vmcb->gs.access_rights = 0x0093;
594 vmcb->ss.selector = 0;
596 vmcb->ss.limit = 0xffff;
597 vmcb->ss.access_rights = 0x0093;
599 vmcb->tr.selector = 0;
601 vmcb->tr.limit = 0xffff;
602 vmcb->tr.access_rights = 0x008b;
604 vmcb->ldtr.selector = 0;
606 vmcb->ldtr.limit = 0xffff;
607 vmcb->ldtr.access_rights = 0x0082;
609 vmcb->gdtr.selector = 0;
611 vmcb->gdtr.limit = 0xffff;
612 vmcb->gdtr.access_rights = 0;
614 vmcb->idtr.selector = 0;
616 vmcb->idtr.limit = 0xffff;
617 vmcb->idtr.access_rights = 0;
619 vmcb->efer = EFER_SVME;
621 /* These MSRs are undefined on reset */
626 vmcb->sysenter_cs = 0;
627 vmcb->sysenter_eip = 0;
628 vmcb->sysenter_esp = 0;
629 vmcb->kerngsbase = 0;
631 vmcb->g_pat = PAT_RESET_VALUE;
633 vmcb->dr7 = 0x00000400;
635 /* Almost all of the guest state changed */
636 vmcb->clean_bits = 0;
638 ok &= svm_set_cell_config(cpu_data->cell, vmcb);
640 /* This is always false, but to be consistent with vmx.c... */
642 panic_printk("FATAL: CPU reset failed\n");
647 void vcpu_skip_emulated_instruction(unsigned int inst_len)
649 struct per_cpu *cpu_data = this_cpu_data();
650 struct vmcb *vmcb = &cpu_data->vmcb;
651 vmcb->rip += inst_len;
654 static void update_efer(struct per_cpu *cpu_data)
656 struct vmcb *vmcb = &cpu_data->vmcb;
657 unsigned long efer = vmcb->efer;
659 if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
664 /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
665 if ((vmcb->efer ^ efer) & EFER_LMA)
669 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
672 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
674 struct per_cpu *cpu_data = this_cpu_data();
675 struct vmcb *vmcb = &cpu_data->vmcb;
677 if (vmcb->efer & EFER_LMA) {
678 pg_structs->root_paging = x86_64_paging;
679 pg_structs->root_table_gphys =
680 vmcb->cr3 & 0x000ffffffffff000UL;
681 } else if ((vmcb->cr0 & X86_CR0_PG) &&
682 !(vmcb->cr4 & X86_CR4_PAE)) {
683 pg_structs->root_paging = i386_paging;
684 pg_structs->root_table_gphys =
685 vmcb->cr3 & 0xfffff000UL;
686 } else if (!(vmcb->cr0 & X86_CR0_PG)) {
688 * Can be in non-paged protected mode as well, but
689 * the translation mechanism will stay the same ayway.
691 pg_structs->root_paging = realmode_paging;
693 * This will make paging_get_guest_pages map the page
694 * that also contains the bootstrap code and, thus, is
695 * always present in a cell.
697 pg_structs->root_table_gphys = 0xff000;
699 printk("FATAL: Unsupported paging mode\n");
705 struct parse_context {
706 unsigned int remaining;
708 unsigned long cs_base;
712 static bool ctx_advance(struct parse_context *ctx,
714 struct guest_paging_structures *pg_structs)
717 ctx->size = ctx->remaining;
718 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
722 ctx->remaining -= ctx->size;
728 static bool x86_parse_mov_to_cr(struct per_cpu *cpu_data,
733 struct guest_paging_structures pg_structs;
734 struct vmcb *vmcb = &cpu_data->vmcb;
735 struct parse_context ctx = {};
736 /* No prefixes are supported yet */
737 u8 opcodes[] = {0x0f, 0x22}, modrm;
741 ctx.remaining = ARRAY_SIZE(opcodes);
742 if (!vcpu_get_guest_paging_structs(&pg_structs))
744 ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
746 if (!ctx_advance(&ctx, &pc, &pg_structs))
749 for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
750 if (*(ctx.inst) != opcodes[n])
752 if (!ctx_advance(&ctx, &pc, &pg_structs))
756 if (!ctx_advance(&ctx, &pc, &pg_structs))
761 if (((modrm & 0x38) >> 3) != reg)
765 *gpr = (modrm & 0x7);
773 * XXX: The only visible reason to have this function (vmx.c consistency
774 * aside) is to prevent cells from setting invalid CD+NW combinations that
775 * result in no more than VMEXIT_INVALID. Maybe we can get along without it
778 static bool svm_handle_cr(struct registers *guest_regs,
779 struct per_cpu *cpu_data)
781 struct vmcb *vmcb = &cpu_data->vmcb;
782 /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
783 unsigned long reg = -1, val, bits;
787 if (!(vmcb->exitinfo1 & (1UL << 63))) {
788 panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
792 reg = vmcb->exitinfo1 & 0x07;
794 if (!x86_parse_mov_to_cr(cpu_data, vmcb->rip, 0, ®)) {
795 panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
804 val = ((unsigned long *)guest_regs)[15 - reg];
806 vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
807 /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
808 bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
809 if ((val ^ vmcb->cr0) & bits)
811 /* TODO: better check for #GP reasons */
812 vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
813 if (val & X86_CR0_PG)
814 update_efer(cpu_data);
815 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
821 static bool svm_handle_msr_read(struct registers *guest_regs,
822 struct per_cpu *cpu_data)
824 switch (guest_regs->rcx) {
826 set_rdmsr_value(guest_regs, cpu_data->vmcb.g_pat);
829 return vcpu_handle_msr_read(guest_regs);
832 vcpu_skip_emulated_instruction(X86_INST_LEN_RDMSR);
836 static bool svm_handle_msr_write(struct registers *guest_regs,
837 struct per_cpu *cpu_data)
839 struct vmcb *vmcb = &cpu_data->vmcb;
840 unsigned long efer, val;
842 switch (guest_regs->rcx) {
844 vmcb->g_pat = get_wrmsr_value(guest_regs);
845 vmcb->clean_bits &= ~CLEAN_BITS_NP;
848 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
849 efer = get_wrmsr_value(guest_regs) | EFER_SVME;
850 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
851 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
854 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
857 val = get_wrmsr_value(guest_regs);
859 * Quick (and very incomplete) guest MTRRs emulation.
861 * For Linux, emulating MTRR Enable bit seems to be enough.
862 * If it is cleared, we set hPAT to all zeroes, effectively
863 * making all NPT-mapped memory UC (see APMv2, Sect. 15.25.8).
865 * Otherwise, default PAT value is restored. This can also
866 * make NPT-mapped memory's type different from what Linux
870 write_msr(MSR_IA32_PAT, PAT_RESET_VALUE);
872 write_msr(MSR_IA32_PAT, 0);
875 return vcpu_handle_msr_write(guest_regs);
878 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
883 * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
884 * be treated separately in svm_handle_avic_access().
886 static bool svm_handle_apic_access(struct registers *guest_regs,
887 struct per_cpu *cpu_data)
889 struct vmcb *vmcb = &cpu_data->vmcb;
890 struct guest_paging_structures pg_structs;
891 unsigned int inst_len, offset;
894 /* The caller is responsible for sanity checks */
895 is_write = !!(vmcb->exitinfo1 & 0x2);
896 offset = vmcb->exitinfo2 - XAPIC_BASE;
901 if (!vcpu_get_guest_paging_structs(&pg_structs))
904 inst_len = apic_mmio_access(guest_regs, cpu_data, vmcb->rip,
905 &pg_structs, offset >> 4, is_write);
909 vcpu_skip_emulated_instruction(inst_len);
913 panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
918 static void dump_guest_regs(struct registers *guest_regs, struct vmcb *vmcb)
920 panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
921 vmcb->rsp, vmcb->rflags);
922 panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
923 guest_regs->rbx, guest_regs->rcx);
924 panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
925 guest_regs->rsi, guest_regs->rdi);
926 panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
927 vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
928 !!(vmcb->efer & EFER_LMA));
929 panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
930 vmcb->cr3, vmcb->cr4);
931 panic_printk("EFER: %p\n", vmcb->efer);
934 static void svm_get_vcpu_pf_intercept(struct per_cpu *cpu_data,
935 struct vcpu_pf_intercept *out)
937 struct vmcb *vmcb = &cpu_data->vmcb;
939 out->phys_addr = vmcb->exitinfo2;
940 out->is_write = !!(vmcb->exitinfo1 & 0x2);
943 static void svm_get_vcpu_io_intercept(struct per_cpu *cpu_data,
944 struct vcpu_io_intercept *out)
946 struct vmcb *vmcb = &cpu_data->vmcb;
947 u64 exitinfo = vmcb->exitinfo1;
949 /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
950 out->port = (exitinfo >> 16) & 0xFFFF;
951 out->size = (exitinfo >> 4) & 0x7;
952 out->in = !!(exitinfo & 0x1);
953 out->inst_len = vmcb->exitinfo2 - vmcb->rip;
954 out->rep_or_str = !!(exitinfo & 0x0c);
957 void vcpu_handle_exit(struct registers *guest_regs, struct per_cpu *cpu_data)
959 struct vmcb *vmcb = &cpu_data->vmcb;
960 struct vcpu_execution_state x_state;
961 struct vcpu_pf_intercept pf;
962 struct vcpu_io_intercept io;
966 /* Restore GS value expected by per_cpu data accessors */
967 write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
969 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
971 * All guest state is marked unmodified; individual handlers must clear
972 * the bits as needed.
974 vmcb->clean_bits = 0xffffffff;
976 switch (vmcb->exitcode) {
978 panic_printk("FATAL: VM-Entry failure, error %d\n",
982 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
983 /* Temporarily enable GIF to consume pending NMI */
984 asm volatile("stgi; clgi" : : : "memory");
985 sipi_vector = x86_handle_events(cpu_data);
986 if (sipi_vector >= 0) {
987 printk("CPU %d received SIPI, vector %x\n",
988 cpu_data->cpu_id, sipi_vector);
989 svm_vcpu_reset(cpu_data, sipi_vector);
990 memset(guest_regs, 0, sizeof(*guest_regs));
992 iommu_check_pending_faults(cpu_data);
995 /* FIXME: We are not intercepting CPUID now */
998 vcpu_vendor_get_execution_state(&x_state);
999 vcpu_handle_hypercall(guest_regs, &x_state);
1001 case VMEXIT_CR0_SEL_WRITE:
1002 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
1003 if (svm_handle_cr(guest_regs, cpu_data))
1007 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
1008 if (!vmcb->exitinfo1)
1009 res = svm_handle_msr_read(guest_regs, cpu_data);
1011 res = svm_handle_msr_write(guest_regs, cpu_data);
1016 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
1017 vmcb->exitinfo2 >= XAPIC_BASE &&
1018 vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
1019 /* APIC access in non-AVIC mode */
1020 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
1021 if (svm_handle_apic_access(guest_regs, cpu_data))
1024 /* General MMIO (IOAPIC, PCI etc) */
1025 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
1026 svm_get_vcpu_pf_intercept(cpu_data, &pf);
1027 if (vcpu_handle_pt_violation(guest_regs, &pf))
1031 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
1032 "error code is %x\n", vmcb->exitinfo2,
1033 vmcb->exitinfo1 & 0xf);
1036 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XSETBV]++;
1037 if ((guest_regs->rax & X86_XCR0_FP) &&
1038 (guest_regs->rax & ~cpuid_eax(0x0d)) == 0 &&
1039 guest_regs->rcx == 0 && guest_regs->rdx == 0) {
1040 vcpu_skip_emulated_instruction(X86_INST_LEN_XSETBV);
1044 : "a" (guest_regs->rax), "c" (0), "d" (0));
1047 panic_printk("FATAL: Invalid xsetbv parameters: "
1048 "xcr[%d] = %x:%x\n", guest_regs->rcx,
1049 guest_regs->rdx, guest_regs->rax);
1052 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
1053 svm_get_vcpu_io_intercept(cpu_data, &io);
1054 if (vcpu_handle_io_access(guest_regs, &io))
1057 /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
1059 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
1060 "exitinfo1 %p exitinfo2 %p\n",
1061 vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
1063 dump_guest_regs(guest_regs, vmcb);
1067 void vcpu_park(struct per_cpu *cpu_data)
1069 struct vmcb *vmcb = &cpu_data->vmcb;
1071 svm_vcpu_reset(cpu_data, APIC_BSP_PSEUDO_SIPI);
1072 /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
1073 vmcb->n_cr3 = paging_hvirt2phys(parked_mode_npt);
1078 void vcpu_nmi_handler(void)
1082 void vcpu_tlb_flush(void)
1084 struct per_cpu *cpu_data = this_cpu_data();
1085 struct vmcb *vmcb = &cpu_data->vmcb;
1087 if (has_flush_by_asid)
1088 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1090 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1093 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1094 unsigned long pc, unsigned int *size)
1096 struct per_cpu *cpu_data = this_cpu_data();
1097 struct vmcb *vmcb = &cpu_data->vmcb;
1098 unsigned long start;
1103 start = vmcb->rip - pc;
1104 if (start < vmcb->bytes_fetched) {
1105 *size = vmcb->bytes_fetched - start;
1106 return &vmcb->guest_bytes[start];
1111 return vcpu_map_inst(pg_structs, pc, size);
1115 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1116 struct vcpu_io_bitmap *iobm)
1118 iobm->data = cell->svm.iopm;
1119 iobm->size = sizeof(cell->svm.iopm);
1122 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1124 struct per_cpu *cpu_data = this_cpu_data();
1126 x_state->efer = cpu_data->vmcb.efer;
1127 x_state->rflags = cpu_data->vmcb.rflags;
1128 x_state->cs = cpu_data->vmcb.cs.selector;
1129 x_state->rip = cpu_data->vmcb.rip;
1132 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1133 void enable_irq(void)
1135 asm volatile("stgi; sti" : : : "memory");
1138 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1139 void disable_irq(void)
1141 asm volatile("cli; clgi" : : : "memory");