2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2013
7 * Jan Kiszka <jan.kiszka@siemens.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #define NULL ((void *)0)
15 #define HEAP_BASE 0x000000
16 #define FSEGMENT_BASE 0x0f0000
17 #define COMM_REGION_BASE 0x100000
19 #define INMATE_CS32 0x8
20 #define INMATE_CS64 0x10
21 #define INMATE_DS32 0x18
23 #define NS_PER_USEC 1000UL
24 #define NS_PER_MSEC 1000000UL
25 #define NS_PER_SEC 1000000000UL
27 #define PAGE_SIZE (4 * 1024ULL)
29 #define BITS_PER_LONG 64
30 #define HUGE_PAGE_SIZE (2 * 1024 * 1024ULL)
32 #define BITS_PER_LONG 32
33 #define HUGE_PAGE_SIZE (4 * 1024 * 1024ULL)
35 #define PAGE_MASK (~(PAGE_SIZE - 1))
36 #define HUGE_PAGE_MASK (~(HUGE_PAGE_SIZE - 1))
38 #define X2APIC_ID 0x802
40 #define PCI_CFG_VENDOR_ID 0x000
41 #define PCI_CFG_DEVICE_ID 0x002
42 #define PCI_CFG_COMMAND 0x004
43 # define PCI_CMD_IO (1 << 0)
44 # define PCI_CMD_MEM (1 << 1)
45 # define PCI_CMD_MASTER (1 << 2)
46 # define PCI_CMD_INTX_OFF (1 << 10)
47 #define PCI_CFG_STATUS 0x006
48 # define PCI_STS_INT (1 << 3)
49 # define PCI_STS_CAPS (1 << 4)
50 #define PCI_CFG_BAR 0x010
51 # define PCI_BAR_64BIT 0x4
52 #define PCI_CFG_CAP_PTR 0x034
54 #define PCI_ID_ANY 0xffff
56 #define PCI_CAP_MSI 0x05
57 #define PCI_CAP_MSIX 0x11
59 #define MSIX_CTRL_ENABLE 0x8000
60 #define MSIX_CTRL_FMASK 0x4000
63 typedef signed char s8;
64 typedef unsigned char u8;
66 typedef signed short s16;
67 typedef unsigned short u16;
69 typedef signed int s32;
70 typedef unsigned int u32;
72 typedef signed long long s64;
73 typedef unsigned long long u64;
87 typedef enum { true=1, false=0 } bool;
89 static inline void cpu_relax(void)
91 asm volatile("rep; nop" : : : "memory");
94 static inline void outb(u8 v, u16 port)
96 asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
99 static inline void outw(u16 v, u16 port)
101 asm volatile("outw %0,%1" : : "a" (v), "dN" (port));
104 static inline void outl(u32 v, u16 port)
106 asm volatile("outl %0,%1" : : "a" (v), "dN" (port));
109 static inline u8 inb(u16 port)
112 asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
116 static inline u16 inw(u16 port)
119 asm volatile("inw %1,%0" : "=a" (v) : "dN" (port));
123 static inline u32 inl(u16 port)
126 asm volatile("inl %1,%0" : "=a" (v) : "dN" (port));
130 static inline u8 mmio_read8(void *address)
132 return *(volatile u8 *)address;
135 static inline u16 mmio_read16(void *address)
137 return *(volatile u16 *)address;
140 static inline u32 mmio_read32(void *address)
144 /* assembly-encoded to match the hypervisor MMIO parser support */
145 asm volatile("movl (%1),%0" : "=r" (value) : "r" (address));
149 static inline u64 mmio_read64(void *address)
151 return *(volatile u64 *)address;
154 static inline void mmio_write8(void *address, u8 value)
156 *(volatile u8 *)address = value;
159 static inline void mmio_write16(void *address, u16 value)
161 *(volatile u16 *)address = value;
164 static inline void mmio_write32(void *address, u32 value)
166 /* assembly-encoded to match the hypervisor MMIO parser support */
167 asm volatile("movl %0,(%1)" : : "r" (value), "r" (address));
170 static inline void mmio_write64(void *address, u64 value)
172 *(volatile u64 *)address = value;
175 static inline u64 read_msr(unsigned int msr)
179 asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
180 return low | ((u64)high << 32);
183 static inline void write_msr(unsigned int msr, u64 val)
187 : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32))
191 static inline unsigned int cpu_id(void)
193 return read_msr(X2APIC_ID);
196 #include <jailhouse/hypercall.h>
198 #define comm_region ((struct jailhouse_comm_region *)COMM_REGION_BASE)
200 extern unsigned int printk_uart_base;
201 void printk(const char *fmt, ...);
203 void *memset(void *s, int c, unsigned long n);
204 void *memcpy(void *d, const void *s, unsigned long n);
206 typedef void(*int_handler_t)(void);
209 void int_set_handler(unsigned int vector, int_handler_t handler);
211 enum ioapic_trigger_mode {
213 TRIGGER_LEVEL_ACTIVE_HIGH = 1 << 15,
214 TRIGGER_LEVEL_ACTIVE_LOW = (1 << 15) | (1 << 13),
217 void ioapic_init(void);
218 void ioapic_pin_set_vector(unsigned int pin,
219 enum ioapic_trigger_mode trigger_mode,
220 unsigned int vector);
222 void inmate_main(void);
224 void hypercall_init(void);
226 unsigned long pm_timer_read(void);
227 void delay_us(unsigned long microsecs);
228 unsigned long apic_timer_init(unsigned int vector);
229 void apic_timer_set(unsigned long timeout_ns);
231 enum map_type { MAP_CACHED, MAP_UNCACHED };
233 void *alloc(unsigned long size, unsigned long align);
234 void map_range(void *start, unsigned long size, enum map_type map_type);
236 u32 pci_read_config(u16 bdf, unsigned int addr, unsigned int size);
237 void pci_write_config(u16 bdf, unsigned int addr, u32 value,
239 int pci_find_device(u16 vendor, u16 device, u16 start_bdf);
240 int pci_find_cap(u16 bdf, u16 cap);
241 void pci_msi_set_vector(u16 bdf, unsigned int vector);
242 void pci_msix_set_vector(u16 bdf, unsigned int vector, u32 index);