hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell.h>
  19 #include <jailhouse/cell-config.h>
  20 #include <jailhouse/control.h>
  21 #include <jailhouse/paging.h>
  22 #include <jailhouse/printk.h>
  23 #include <jailhouse/processor.h>
  24 #include <jailhouse/string.h>
  25 #include <jailhouse/utils.h>
  26 #include <asm/apic.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 /* IOPM size: two 4-K pages + 3 bits */
  43 #define IOPM_PAGES              3
  44
  45 static bool has_avic, has_assists, has_flush_by_asid;
  46
  47 static const struct segment invalid_seg;
  48
  49 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  50
  51 /* bit cleared: direct access allowed */
  52 // TODO: convert to whitelist
  53 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  54         [ SVM_MSRPM_0000 ] = {
  55                 [      0/4 ...  0x017/4 ] = 0,
  56                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  57                 [  0x01c/4 ...  0x1ff/4 ] = 0,
  58                 [  0x200/4 ...  0x273/4 ] = 0xaa, /* 0x200 - 0x273 (w) */
  59                 [  0x274/4 ...  0x277/4 ] = 0xea, /* 0x274 - 0x276 (w), 0x277 (rw) */
  60                 [  0x278/4 ...  0x2fb/4 ] = 0,
  61                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  62                 [  0x300/4 ...  0x7ff/4 ] = 0,
  63                 /* x2APIC MSRs - emulated if not present */
  64                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  65                 [  0x804/4 ...  0x807/4 ] = 0,
  66                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  67                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  68                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  69                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  70                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  71                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  72                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  73                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  74                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  75                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  76                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  77                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  78                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  79                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  80                 [  0x840/4 ... 0x1fff/4 ] = 0,
  81         },
  82         [ SVM_MSRPM_C000 ] = {
  83                 [      0/4 ...  0x07f/4 ] = 0,
  84                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  85                 [  0x084/4 ... 0x1fff/4 ] = 0
  86         },
  87         [ SVM_MSRPM_C001 ] = {
  88                 [      0/4 ... 0x1fff/4 ] = 0,
  89         },
  90         [ SVM_MSRPM_RESV ] = {
  91                 [      0/4 ... 0x1fff/4 ] = 0,
  92         }
  93 };
  94
  95 /* This page is mapped so the code begins at 0x000ffff0 */
  96 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  97         [0xff0] = 0xfa, /* 1: cli */
  98         [0xff1] = 0xf4, /*    hlt */
  99         [0xff2] = 0xeb,
 100         [0xff3] = 0xfc  /*    jmp 1b */
 101 };
 102
 103 static void *parked_mode_npt;
 104
 105 static void *avic_page;
 106
 107 static int svm_check_features(void)
 108 {
 109         /* SVM is available */
 110         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 111                 return trace_error(-ENODEV);
 112
 113         /* Nested paging */
 114         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 115                 return trace_error(-EIO);
 116
 117         /* Decode assists */
 118         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 119                 has_assists = true;
 120
 121         /* AVIC support */
 122         /* FIXME: Jailhouse support is incomplete so far
 123         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 124                 has_avic = true; */
 125
 126         /* TLB Flush by ASID support */
 127         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 128                 has_flush_by_asid = true;
 129
 130         return 0;
 131 }
 132
 133 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 134                                      const struct desc_table_reg *dtr)
 135 {
 136         svm_segment->base = dtr->base;
 137         svm_segment->limit = dtr->limit & 0xffff;
 138 }
 139
 140 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 141                                          const struct segment *segment)
 142 {
 143         svm_segment->selector = segment->selector;
 144         svm_segment->access_rights = ((segment->access_rights & 0xf000) >> 4) |
 145                 (segment->access_rights & 0x00ff);
 146         svm_segment->limit = segment->limit;
 147         svm_segment->base = segment->base;
 148 }
 149
 150 static void svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 151 {
 152         vmcb->iopm_base_pa = paging_hvirt2phys(cell->arch.svm.iopm);
 153         vmcb->n_cr3 = paging_hvirt2phys(cell->arch.svm.npt_structs.root_table);
 154 }
 155
 156 static void vmcb_setup(struct per_cpu *cpu_data)
 157 {
 158         struct vmcb *vmcb = &cpu_data->vmcb;
 159
 160         memset(vmcb, 0, sizeof(struct vmcb));
 161
 162         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 163         vmcb->cr3 = cpu_data->linux_cr3;
 164         vmcb->cr4 = cpu_data->linux_cr4;
 165
 166         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 167         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 168         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 169         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 170         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 171         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 172         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 173         set_svm_segment_from_segment(&vmcb->ldtr, &invalid_seg);
 174
 175         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 176         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 177
 178         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 179
 180         vmcb->rflags = 0x02;
 181         /* Indicate success to the caller of arch_entry */
 182         vmcb->rax = 0;
 183         vmcb->rsp = cpu_data->linux_sp +
 184                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 185         vmcb->rip = cpu_data->linux_ip;
 186
 187         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 188         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 189         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 190         vmcb->star = read_msr(MSR_STAR);
 191         vmcb->lstar = read_msr(MSR_LSTAR);
 192         vmcb->cstar = read_msr(MSR_CSTAR);
 193         vmcb->sfmask = read_msr(MSR_SFMASK);
 194         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 195
 196         vmcb->dr6 = 0x00000ff0;
 197         vmcb->dr7 = 0x00000400;
 198
 199         /* Make the hypervisor visible */
 200         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 201
 202         vmcb->g_pat = cpu_data->pat;
 203
 204         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 205         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 206         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID;
 207         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 208         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 209         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 210
 211         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 212         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 213
 214         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 215
 216         vmcb->np_enable = 1;
 217         /* No more than one guest owns the CPU */
 218         vmcb->guest_asid = 1;
 219
 220         /* TODO: Setup AVIC */
 221
 222         /* Explicitly mark all of the state as new */
 223         vmcb->clean_bits = 0;
 224
 225         svm_set_cell_config(cpu_data->cell, vmcb);
 226 }
 227
 228 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 229                                      unsigned long gphys,
 230                                      unsigned long flags)
 231 {
 232         return paging_virt2phys(&cpu_data->cell->arch.svm.npt_structs,
 233                         gphys, flags);
 234 }
 235
 236 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 237 {
 238         /* See APMv2, Section 15.25.5 */
 239         *pte = (next_pt & 0x000ffffffffff000UL) |
 240                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 241 }
 242
 243 int vcpu_vendor_init(void)
 244 {
 245         struct paging_structures parking_pt;
 246         unsigned long vm_cr;
 247         int err, n;
 248
 249         err = svm_check_features();
 250         if (err)
 251                 return err;
 252
 253         vm_cr = read_msr(MSR_VM_CR);
 254         if (vm_cr & VM_CR_SVMDIS)
 255                 /* SVM disabled in BIOS */
 256                 return trace_error(-EPERM);
 257
 258         /* Nested paging is the same as the native one */
 259         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 260         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 261                 npt_paging[n].set_next_pt = npt_set_next_pt;
 262
 263         /* Map guest parking code (shared between cells and CPUs) */
 264         parking_pt.root_paging = npt_paging;
 265         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 266         if (!parked_mode_npt)
 267                 return -ENOMEM;
 268         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 269                             PAGE_SIZE, 0x000ff000,
 270                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 271                             PAGING_NON_COHERENT);
 272         if (err)
 273                 return err;
 274
 275         /* This is always false for AMD now (except in nested SVM);
 276            see Sect. 16.3.1 in APMv2 */
 277         if (using_x2apic) {
 278                 /* allow direct x2APIC access except for ICR writes */
 279                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 280                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 281                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 282         } else {
 283                 if (has_avic) {
 284                         avic_page = page_alloc(&remap_pool, 1);
 285                         if (!avic_page)
 286                                 return trace_error(-ENOMEM);
 287                 }
 288         }
 289
 290         return vcpu_cell_init(&root_cell);
 291 }
 292
 293 int vcpu_vendor_cell_init(struct cell *cell)
 294 {
 295         int err = -ENOMEM;
 296         u64 flags;
 297
 298         /* allocate iopm  */
 299         cell->arch.svm.iopm = page_alloc(&mem_pool, IOPM_PAGES);
 300         if (!cell->arch.svm.iopm)
 301                 return err;
 302
 303         /* build root NPT of cell */
 304         cell->arch.svm.npt_structs.root_paging = npt_paging;
 305         cell->arch.svm.npt_structs.root_table =
 306                 (page_table_t)cell->arch.root_table_page;
 307
 308         if (!has_avic) {
 309                 /*
 310                  * Map xAPIC as is; reads are passed, writes are trapped.
 311                  */
 312                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 313                 err = paging_create(&cell->arch.svm.npt_structs, XAPIC_BASE,
 314                                     PAGE_SIZE, XAPIC_BASE,
 315                                     flags,
 316                                     PAGING_NON_COHERENT);
 317         } else {
 318                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 319                 err = paging_create(&cell->arch.svm.npt_structs,
 320                                     paging_hvirt2phys(avic_page),
 321                                     PAGE_SIZE, XAPIC_BASE,
 322                                     flags,
 323                                     PAGING_NON_COHERENT);
 324         }
 325         if (err)
 326                 goto err_free_iopm;
 327
 328         return 0;
 329
 330 err_free_iopm:
 331         page_free(&mem_pool, cell->arch.svm.iopm, 3);
 332
 333         return err;
 334 }
 335
 336 int vcpu_map_memory_region(struct cell *cell,
 337                            const struct jailhouse_memory *mem)
 338 {
 339         u64 phys_start = mem->phys_start;
 340         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 341
 342         if (mem->flags & JAILHOUSE_MEM_READ)
 343                 flags |= PAGE_FLAG_PRESENT;
 344         if (mem->flags & JAILHOUSE_MEM_WRITE)
 345                 flags |= PAGE_FLAG_RW;
 346         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 347                 flags |= PAGE_FLAG_NOEXECUTE;
 348         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 349                 phys_start = paging_hvirt2phys(&cell->comm_page);
 350
 351         return paging_create(&cell->arch.svm.npt_structs, phys_start, mem->size,
 352                              mem->virt_start, flags, PAGING_NON_COHERENT);
 353 }
 354
 355 int vcpu_unmap_memory_region(struct cell *cell,
 356                              const struct jailhouse_memory *mem)
 357 {
 358         return paging_destroy(&cell->arch.svm.npt_structs, mem->virt_start,
 359                               mem->size, PAGING_NON_COHERENT);
 360 }
 361
 362 void vcpu_vendor_cell_exit(struct cell *cell)
 363 {
 364         paging_destroy(&cell->arch.svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 365                        PAGING_NON_COHERENT);
 366         page_free(&mem_pool, cell->arch.svm.iopm, 3);
 367 }
 368
 369 int vcpu_init(struct per_cpu *cpu_data)
 370 {
 371         unsigned long efer;
 372         int err;
 373
 374         err = svm_check_features();
 375         if (err)
 376                 return err;
 377
 378         efer = read_msr(MSR_EFER);
 379         if (efer & EFER_SVME)
 380                 return trace_error(-EBUSY);
 381
 382         efer |= EFER_SVME;
 383         write_msr(MSR_EFER, efer);
 384
 385         cpu_data->svm_state = SVMON;
 386
 387         vmcb_setup(cpu_data);
 388
 389         /*
 390          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 391          * set the values of reserved bits to the values found during the
 392          * previous CR0 read."
 393          * But we want to avoid surprises with new features unknown to us but
 394          * set by Linux. So check if any assumed revered bit was set and bail
 395          * out if so.
 396          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 397          */
 398         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 399                 return -EIO;
 400
 401         /* bring CR0 and CR4 into well-defined states */
 402         write_cr0(X86_CR0_HOST_STATE);
 403         write_cr4(X86_CR4_HOST_STATE);
 404
 405         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 406
 407         return 0;
 408 }
 409
 410 void vcpu_exit(struct per_cpu *cpu_data)
 411 {
 412         unsigned long efer;
 413
 414         if (cpu_data->svm_state == SVMOFF)
 415                 return;
 416
 417         cpu_data->svm_state = SVMOFF;
 418
 419         /* We are leaving - set the GIF */
 420         asm volatile ("stgi" : : : "memory");
 421
 422         efer = read_msr(MSR_EFER);
 423         efer &= ~EFER_SVME;
 424         write_msr(MSR_EFER, efer);
 425
 426         write_msr(MSR_VM_HSAVE_PA, 0);
 427 }
 428
 429 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 430 {
 431         unsigned long vmcb_pa, host_stack;
 432
 433         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 434         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 435
 436         /* We enter Linux at the point arch_entry would return to as well.
 437          * rax is cleared to signal success to the caller. */
 438         asm volatile(
 439                 "clgi\n\t"
 440                 "mov (%%rdi),%%r15\n\t"
 441                 "mov 0x8(%%rdi),%%r14\n\t"
 442                 "mov 0x10(%%rdi),%%r13\n\t"
 443                 "mov 0x18(%%rdi),%%r12\n\t"
 444                 "mov 0x20(%%rdi),%%rbx\n\t"
 445                 "mov 0x28(%%rdi),%%rbp\n\t"
 446                 "mov %2,%%rsp\n\t"
 447                 "vmload %%rax\n\t"
 448                 "jmp svm_vmentry"
 449                 : /* no output */
 450                 : "D" (cpu_data->linux_reg), "a" (vmcb_pa), "m" (host_stack));
 451         __builtin_unreachable();
 452 }
 453
 454 void __attribute__((noreturn)) vcpu_deactivate_vmm(void)
 455 {
 456         struct per_cpu *cpu_data = this_cpu_data();
 457         struct vmcb *vmcb = &cpu_data->vmcb;
 458         unsigned long *stack = (unsigned long *)vmcb->rsp;
 459         unsigned long linux_ip = vmcb->rip;
 460
 461         cpu_data->linux_cr0 = vmcb->cr0;
 462         cpu_data->linux_cr3 = vmcb->cr3;
 463
 464         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 465         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 466         cpu_data->linux_idtr.base = vmcb->idtr.base;
 467         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 468
 469         cpu_data->linux_cs.selector = vmcb->cs.selector;
 470
 471         asm volatile("str %0" : "=m" (cpu_data->linux_tss.selector));
 472
 473         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 474         cpu_data->linux_fs.base = read_msr(MSR_FS_BASE);
 475         cpu_data->linux_gs.base = vmcb->gs.base;
 476
 477         cpu_data->linux_ds.selector = vmcb->ds.selector;
 478         cpu_data->linux_es.selector = vmcb->es.selector;
 479
 480         asm volatile("mov %%fs,%0" : "=m" (cpu_data->linux_fs.selector));
 481         asm volatile("mov %%gs,%0" : "=m" (cpu_data->linux_gs.selector));
 482
 483         arch_cpu_restore(cpu_data, 0);
 484
 485         stack--;
 486         *stack = linux_ip;
 487
 488         asm volatile (
 489                 "mov %%rbx,%%rsp\n\t"
 490                 "pop %%r15\n\t"
 491                 "pop %%r14\n\t"
 492                 "pop %%r13\n\t"
 493                 "pop %%r12\n\t"
 494                 "pop %%r11\n\t"
 495                 "pop %%r10\n\t"
 496                 "pop %%r9\n\t"
 497                 "pop %%r8\n\t"
 498                 "pop %%rdi\n\t"
 499                 "pop %%rsi\n\t"
 500                 "pop %%rbp\n\t"
 501                 "add $8,%%rsp\n\t"
 502                 "pop %%rbx\n\t"
 503                 "pop %%rdx\n\t"
 504                 "pop %%rcx\n\t"
 505                 "mov %%rax,%%rsp\n\t"
 506                 "xor %%rax,%%rax\n\t"
 507                 "ret"
 508                 : : "a" (stack), "b" (&cpu_data->guest_regs));
 509         __builtin_unreachable();
 510 }
 511
 512 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 513 {
 514         static const struct svm_segment dataseg_reset_state = {
 515                 .selector = 0,
 516                 .base = 0,
 517                 .limit = 0xffff,
 518                 .access_rights = 0x0093,
 519         };
 520         static const struct svm_segment dtr_reset_state = {
 521                 .selector = 0,
 522                 .base = 0,
 523                 .limit = 0xffff,
 524                 .access_rights = 0,
 525         };
 526         struct vmcb *vmcb = &cpu_data->vmcb;
 527         unsigned long val;
 528
 529         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 530         vmcb->cr3 = 0;
 531         vmcb->cr4 = 0;
 532
 533         vmcb->rflags = 0x02;
 534
 535         val = 0;
 536         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 537                 val = 0xfff0;
 538                 sipi_vector = 0xf0;
 539         }
 540         vmcb->rip = val;
 541         vmcb->rsp = 0;
 542
 543         vmcb->cs.selector = sipi_vector << 8;
 544         vmcb->cs.base = sipi_vector << 12;
 545         vmcb->cs.limit = 0xffff;
 546         vmcb->cs.access_rights = 0x009b;
 547
 548         vmcb->ds = dataseg_reset_state;
 549         vmcb->es = dataseg_reset_state;
 550         vmcb->fs = dataseg_reset_state;
 551         vmcb->gs = dataseg_reset_state;
 552         vmcb->ss = dataseg_reset_state;
 553
 554         vmcb->tr.selector = 0;
 555         vmcb->tr.base = 0;
 556         vmcb->tr.limit = 0xffff;
 557         vmcb->tr.access_rights = 0x008b;
 558
 559         vmcb->ldtr.selector = 0;
 560         vmcb->ldtr.base = 0;
 561         vmcb->ldtr.limit = 0xffff;
 562         vmcb->ldtr.access_rights = 0x0082;
 563
 564         vmcb->gdtr = dtr_reset_state;
 565         vmcb->idtr = dtr_reset_state;
 566
 567         vmcb->efer = EFER_SVME;
 568
 569         /* These MSRs are undefined on reset */
 570         vmcb->star = 0;
 571         vmcb->lstar = 0;
 572         vmcb->cstar = 0;
 573         vmcb->sfmask = 0;
 574         vmcb->sysenter_cs = 0;
 575         vmcb->sysenter_eip = 0;
 576         vmcb->sysenter_esp = 0;
 577         vmcb->kerngsbase = 0;
 578
 579         vmcb->dr7 = 0x00000400;
 580
 581         /* Almost all of the guest state changed */
 582         vmcb->clean_bits = 0;
 583
 584         svm_set_cell_config(cpu_data->cell, vmcb);
 585
 586         asm volatile(
 587                 "vmload %%rax"
 588                 : : "a" (paging_hvirt2phys(vmcb)) : "memory");
 589         /* vmload overwrites GS_BASE - restore the host state */
 590         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 591 }
 592
 593 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 594 {
 595         this_cpu_data()->vmcb.rip += inst_len;
 596 }
 597
 598 static void update_efer(struct vmcb *vmcb)
 599 {
 600         unsigned long efer = vmcb->efer;
 601
 602         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 603                 return;
 604
 605         efer |= EFER_LMA;
 606
 607         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 608         if ((vmcb->efer ^ efer) & EFER_LMA)
 609                 vcpu_tlb_flush();
 610
 611         vmcb->efer = efer;
 612         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 613 }
 614
 615 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 616 {
 617         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 618
 619         if (vmcb->efer & EFER_LMA) {
 620                 pg_structs->root_paging = x86_64_paging;
 621                 pg_structs->root_table_gphys =
 622                         vmcb->cr3 & 0x000ffffffffff000UL;
 623         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 624                    !(vmcb->cr4 & X86_CR4_PAE)) {
 625                 pg_structs->root_paging = i386_paging;
 626                 pg_structs->root_table_gphys =
 627                         vmcb->cr3 & 0xfffff000UL;
 628         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 629                 /*
 630                  * Can be in non-paged protected mode as well, but
 631                  * the translation mechanism will stay the same ayway.
 632                  */
 633                 pg_structs->root_paging = realmode_paging;
 634                 /*
 635                  * This will make paging_get_guest_pages map the page
 636                  * that also contains the bootstrap code and, thus, is
 637                  * always present in a cell.
 638                  */
 639                 pg_structs->root_table_gphys = 0xff000;
 640         } else {
 641                 printk("FATAL: Unsupported paging mode\n");
 642                 return false;
 643         }
 644         return true;
 645 }
 646
 647 void vcpu_vendor_set_guest_pat(unsigned long val)
 648 {
 649         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 650
 651         vmcb->g_pat = val;
 652         vmcb->clean_bits &= ~CLEAN_BITS_NP;
 653 }
 654
 655 struct parse_context {
 656         unsigned int remaining;
 657         unsigned int size;
 658         unsigned long cs_base;
 659         const u8 *inst;
 660 };
 661
 662 static bool ctx_advance(struct parse_context *ctx,
 663                         unsigned long *pc,
 664                         struct guest_paging_structures *pg_structs)
 665 {
 666         if (!ctx->size) {
 667                 ctx->size = ctx->remaining;
 668                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 669                                           &ctx->size);
 670                 if (!ctx->inst)
 671                         return false;
 672                 ctx->remaining -= ctx->size;
 673                 *pc += ctx->size;
 674         }
 675         return true;
 676 }
 677
 678 static bool svm_parse_mov_to_cr(struct vmcb *vmcb, unsigned long pc,
 679                                 unsigned char reg, unsigned long *gpr)
 680 {
 681         struct guest_paging_structures pg_structs;
 682         struct parse_context ctx = {};
 683         /* No prefixes are supported yet */
 684         u8 opcodes[] = {0x0f, 0x22}, modrm;
 685         int n;
 686
 687         ctx.remaining = ARRAY_SIZE(opcodes);
 688         if (!vcpu_get_guest_paging_structs(&pg_structs))
 689                 return false;
 690         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 691
 692         if (!ctx_advance(&ctx, &pc, &pg_structs))
 693                 return false;
 694
 695         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++)
 696                 if (*(ctx.inst) != opcodes[n] ||
 697                     !ctx_advance(&ctx, &pc, &pg_structs))
 698                         return false;
 699
 700         if (!ctx_advance(&ctx, &pc, &pg_structs))
 701                 return false;
 702
 703         modrm = *(ctx.inst);
 704
 705         if (((modrm & 0x38) >> 3) != reg)
 706                 return false;
 707
 708         if (gpr)
 709                 *gpr = (modrm & 0x7);
 710
 711         return true;
 712 }
 713
 714 /*
 715  * XXX: The only visible reason to have this function (vmx.c consistency
 716  * aside) is to prevent cells from setting invalid CD+NW combinations that
 717  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 718  * altogether?
 719  */
 720 static bool svm_handle_cr(struct per_cpu *cpu_data)
 721 {
 722         struct vmcb *vmcb = &cpu_data->vmcb;
 723         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 724         unsigned long reg = -1, val, bits;
 725
 726         if (has_assists) {
 727                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 728                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 729                         return false;
 730                 }
 731                 reg = vmcb->exitinfo1 & 0x07;
 732         } else {
 733                 if (!svm_parse_mov_to_cr(vmcb, vmcb->rip, 0, &reg)) {
 734                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 735                         return false;
 736                 }
 737         }
 738
 739         if (reg == 4)
 740                 val = vmcb->rsp;
 741         else
 742                 val = cpu_data->guest_regs.by_index[15 - reg];
 743
 744         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 745         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 746         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 747         if ((val ^ vmcb->cr0) & bits)
 748                 vcpu_tlb_flush();
 749         /* TODO: better check for #GP reasons */
 750         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 751         if (val & X86_CR0_PG)
 752                 update_efer(vmcb);
 753         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 754
 755         return true;
 756 }
 757
 758 static bool svm_handle_msr_write(struct per_cpu *cpu_data)
 759 {
 760         struct vmcb *vmcb = &cpu_data->vmcb;
 761         unsigned long efer;
 762
 763         if (cpu_data->guest_regs.rcx == MSR_EFER) {
 764                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 765                 efer = get_wrmsr_value(&cpu_data->guest_regs) | EFER_SVME;
 766                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 767                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 768                         vcpu_tlb_flush();
 769                 vmcb->efer = efer;
 770                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 771                 vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 772                 return true;
 773         }
 774
 775         return vcpu_handle_msr_write();
 776 }
 777
 778 /*
 779  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 780  * be treated separately in svm_handle_avic_access().
 781  */
 782 static bool svm_handle_apic_access(struct vmcb *vmcb)
 783 {
 784         struct guest_paging_structures pg_structs;
 785         unsigned int inst_len, offset;
 786         bool is_write;
 787
 788         /* The caller is responsible for sanity checks */
 789         is_write = !!(vmcb->exitinfo1 & 0x2);
 790         offset = vmcb->exitinfo2 - XAPIC_BASE;
 791
 792         if (offset & 0x00f)
 793                 goto out_err;
 794
 795         if (!vcpu_get_guest_paging_structs(&pg_structs))
 796                 goto out_err;
 797
 798         inst_len = apic_mmio_access(vmcb->rip, &pg_structs, offset >> 4,
 799                                     is_write);
 800         if (!inst_len)
 801                 goto out_err;
 802
 803         vcpu_skip_emulated_instruction(inst_len);
 804         return true;
 805
 806 out_err:
 807         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 808                      offset, is_write);
 809         return false;
 810 }
 811
 812 static void dump_guest_regs(union registers *guest_regs, struct vmcb *vmcb)
 813 {
 814         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 815                      vmcb->rsp, vmcb->rflags);
 816         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 817                      guest_regs->rbx, guest_regs->rcx);
 818         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 819                      guest_regs->rsi, guest_regs->rdi);
 820         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 821                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 822                      !!(vmcb->efer & EFER_LMA));
 823         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 824                      vmcb->cr3, vmcb->cr4);
 825         panic_printk("EFER: %p\n", vmcb->efer);
 826 }
 827
 828 void vcpu_vendor_get_io_intercept(struct vcpu_io_intercept *io)
 829 {
 830         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 831         u64 exitinfo = vmcb->exitinfo1;
 832
 833         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 834         io->port = (exitinfo >> 16) & 0xFFFF;
 835         io->size = (exitinfo >> 4) & 0x7;
 836         io->in = !!(exitinfo & 0x1);
 837         io->inst_len = vmcb->exitinfo2 - vmcb->rip;
 838         io->rep_or_str = !!(exitinfo & 0x0c);
 839 }
 840
 841 void vcpu_vendor_get_mmio_intercept(struct vcpu_mmio_intercept *mmio)
 842 {
 843         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 844
 845         mmio->phys_addr = vmcb->exitinfo2;
 846         mmio->is_write = !!(vmcb->exitinfo1 & 0x2);
 847 }
 848
 849 void vcpu_handle_exit(struct per_cpu *cpu_data)
 850 {
 851         struct vmcb *vmcb = &cpu_data->vmcb;
 852         bool res = false;
 853         int sipi_vector;
 854
 855         vmcb->gs.base = read_msr(MSR_GS_BASE);
 856
 857         /* Restore GS value expected by per_cpu data accessors */
 858         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 859
 860         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 861         /*
 862          * All guest state is marked unmodified; individual handlers must clear
 863          * the bits as needed.
 864          */
 865         vmcb->clean_bits = 0xffffffff;
 866
 867         switch (vmcb->exitcode) {
 868         case VMEXIT_INVALID:
 869                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 870                              vmcb->exitcode);
 871                 break;
 872         case VMEXIT_NMI:
 873                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 874                 /* Temporarily enable GIF to consume pending NMI */
 875                 asm volatile("stgi; clgi" : : : "memory");
 876                 sipi_vector = x86_handle_events(cpu_data);
 877                 if (sipi_vector >= 0) {
 878                         printk("CPU %d received SIPI, vector %x\n",
 879                                cpu_data->cpu_id, sipi_vector);
 880                         svm_vcpu_reset(cpu_data, sipi_vector);
 881                         vcpu_reset(sipi_vector == APIC_BSP_PSEUDO_SIPI);
 882                 }
 883                 iommu_check_pending_faults();
 884                 goto vmentry;
 885         case VMEXIT_VMMCALL:
 886                 vcpu_handle_hypercall();
 887                 goto vmentry;
 888         case VMEXIT_CR0_SEL_WRITE:
 889                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
 890                 if (svm_handle_cr(cpu_data))
 891                         goto vmentry;
 892                 break;
 893         case VMEXIT_CPUID:
 894                 vcpu_handle_cpuid();
 895                 goto vmentry;
 896         case VMEXIT_MSR:
 897                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
 898                 if (!vmcb->exitinfo1)
 899                         res = vcpu_handle_msr_read();
 900                 else
 901                         res = svm_handle_msr_write(cpu_data);
 902                 if (res)
 903                         goto vmentry;
 904                 break;
 905         case VMEXIT_NPF:
 906                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
 907                      vmcb->exitinfo2 >= XAPIC_BASE &&
 908                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
 909                         /* APIC access in non-AVIC mode */
 910                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
 911                         if (svm_handle_apic_access(vmcb))
 912                                 goto vmentry;
 913                 } else {
 914                         /* General MMIO (IOAPIC, PCI etc) */
 915                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
 916                         if (vcpu_handle_mmio_access())
 917                                 goto vmentry;
 918                 }
 919                 break;
 920         case VMEXIT_XSETBV:
 921                 if (vcpu_handle_xsetbv())
 922                         goto vmentry;
 923                 break;
 924         case VMEXIT_IOIO:
 925                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
 926                 if (vcpu_handle_io_access())
 927                         goto vmentry;
 928                 break;
 929         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
 930         default:
 931                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
 932                              "exitinfo1 %p exitinfo2 %p\n",
 933                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
 934         }
 935         dump_guest_regs(&cpu_data->guest_regs, vmcb);
 936         panic_park();
 937
 938 vmentry:
 939         write_msr(MSR_GS_BASE, vmcb->gs.base);
 940 }
 941
 942 void vcpu_park(void)
 943 {
 944         svm_vcpu_reset(this_cpu_data(), APIC_BSP_PSEUDO_SIPI);
 945         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
 946         this_cpu_data()->vmcb.n_cr3 = paging_hvirt2phys(parked_mode_npt);
 947
 948         vcpu_tlb_flush();
 949 }
 950
 951 void vcpu_nmi_handler(void)
 952 {
 953 }
 954
 955 void vcpu_tlb_flush(void)
 956 {
 957         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 958
 959         if (has_flush_by_asid)
 960                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
 961         else
 962                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
 963 }
 964
 965 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
 966                               unsigned long pc, unsigned int *size)
 967 {
 968         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 969         unsigned long start;
 970
 971         if (has_assists) {
 972                 if (!*size)
 973                         return NULL;
 974                 start = vmcb->rip - pc;
 975                 if (start < vmcb->bytes_fetched) {
 976                         *size = vmcb->bytes_fetched - start;
 977                         return &vmcb->guest_bytes[start];
 978                 } else {
 979                         return NULL;
 980                 }
 981         } else {
 982                 return vcpu_map_inst(pg_structs, pc, size);
 983         }
 984 }
 985
 986 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
 987                                     struct vcpu_io_bitmap *iobm)
 988 {
 989         iobm->data = cell->arch.svm.iopm;
 990         iobm->size = IOPM_PAGES * PAGE_SIZE;
 991 }
 992
 993 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
 994 {
 995         struct vmcb *vmcb = &this_cpu_data()->vmcb;
 996
 997         x_state->efer = vmcb->efer;
 998         x_state->rflags = vmcb->rflags;
 999         x_state->cs = vmcb->cs.selector;
1000         x_state->rip = vmcb->rip;
1001 }
1002
1003 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1004 void enable_irq(void)
1005 {
1006         asm volatile("stgi; sti" : : : "memory");
1007 }
1008
1009 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1010 void disable_irq(void)
1011 {
1012         asm volatile("cli; clgi" : : : "memory");
1013 }