]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/blob - .gitmodules
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / .gitmodules
1 [submodule "can-benchmark"]
2         path = can-benchmark
3         url = git@rtime.felk.cvut.cz:/can-benchmark.git