]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/history - software/miniterm.py
projects / fpga / virtex2 / uart.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Peripheral connected to the quadcount module and an incremental encoder. Interrupt...
[fpga/virtex2/uart.git] / software / miniterm.py
2011-01-09 Vladimir BurianCopied all needed files. blob | commitdiff | raw
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board