]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/commit
projects / fpga / virtex2 / uart.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d90e546) | patch
+ README master
authorVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 13 Feb 2011 16:26:13 +0000 (17:26 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 13 Feb 2011 16:26:56 +0000 (17:26 +0100)
commitc28620b45c6318253d70248e6872ea7ce49427a1
treed9f73d36c8ae6fd2c68b6b15c0fbb821a44e14bctree | snapshot
parentd90e54632ccf2cc286e1c33c802211e7f7ebdc08commit | diff
+ README
README [new file with mode: 0644] blob
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board