+ Quadcount submodule

[fpga/virtex2/uart.git] / openMSP430_uart.vhd

diff --git a/openMSP430_uart.vhd b/openMSP430_uart.vhd
index 3da87209ca80617a5c27c90dc353180b08051e0a..b6e3eceae7e709a5640399e47d2976b297d2245e 100644 (file)
--- a/openMSP430_uart.vhd
+++ b/openMSP430_uart.vhd
@@ -7,8 +7,9 @@ entity openMSP430_uart is
   port (
     CLK_24MHz: in std_logic;
     RESET: in std_logic;
-    DISPLAY1: out std_logic_vector(6 downto 0);
-    DISPLAY2: out std_logic_vector(6 downto 0)
+
+    RXD : out std_logic;
+    TXD : in std_logic
   );
 end openMSP430_uart;
 
@@ -180,6 +181,9 @@ architecture rtl of openMSP430_uart is
   signal gpio_per_dout : std_logic_vector (15 downto 0);
   signal timerA_per_dout : std_logic_vector (15 downto 0);
 
+  signal irq_ta0 : std_logic;
+  signal irq_ta1 : std_logic;
+
 --------------------------------------------------------------------------------
 
 begin
@@ -191,7 +195,7 @@ begin
     dmem_cen      => dmem_cen,
     dmem_din      => dmem_din,
     dmem_wen      => dmem_wen,
-    irq_acc       => open,
+    irq_acc       => irq_acc,
     mclk          => mclk,
     per_addr      => per_addr,
     per_din       => per_din,
@@ -207,7 +211,7 @@ begin
     dbg_uart_rxd  => '0',
     dco_clk       => CLK_24MHz,
     dmem_dout     => dmem_dout,
-    irq           => (others => '0'),
+    irq           => irq,
     lfxt_clk      => '0',
     nmi           => '0',
     per_dout      => per_dout,
@@ -264,12 +268,12 @@ begin
     port map (
       irq_port1 => open,
       irq_port2 => open,
-      p1_dout (6 downto 0) => DISPLAY1,
-      p1_dout (7) => open,
+      p1_dout (7 downto 2) => open,
+      p1_dout (1) => RXD,
+      p1_dout (0) => open,
       p1_dout_en => open,
       p1_sel => open,
-      p2_dout (6 downto 0) => DISPLAY2,
-      p2_dout (7) => open,
+      p2_dout => open,
       p2_dout_en => open,
       p2_sel => open,
       p3_dout => open,
@@ -300,8 +304,8 @@ begin
     );
 
   omsp_timerA_0 : omsp_timerA port map (
-    irq_ta0     => open,
-    irq_ta1     => open,
+    irq_ta0     => irq_ta0,
+    irq_ta1     => irq_ta1,
     per_dout    => timerA_per_dout,
     ta_out0     => open,
     ta_out0_en  => open,
@@ -313,7 +317,7 @@ begin
     aclk_en     => aclk_en,
     dbg_freeze  => '0',
     inclk       => '0',
-    irq_ta0_acc => '0',
+    irq_ta0_acc => irq_acc (9),
     mclk        => mclk,
     per_addr    => per_addr,
     per_din     => per_din,
@@ -322,7 +326,7 @@ begin
     puc         => puc,
     smclk_en    => smclk_en,
     ta_cci0a    => '0',
-    ta_cci0b    => '0',
+    ta_cci0b    => TXD,
     ta_cci1a    => '0',
     ta_cci1b    => '0',
     ta_cci2a    => '0',
@@ -334,5 +338,9 @@ begin
 
   per_dout <=  gpio_per_dout or timerA_per_dout;
   
+  irq <= (9 => irq_ta0,
+          8 => irq_ta1,
+          others => '0');
+  
 end rtl;