PWM test added to the software.

[fpga/virtex2/uart.git] / openMSP430_uart.ucf

diff --git a/openMSP430_uart.ucf b/openMSP430_uart.ucf
index e28d6b55dcddfd0bef00ca09c9a9d6a9d12f564e..a17400a21179e264a83c226fac133f23db334841 100644 (file)
--- a/openMSP430_uart.ucf
+++ b/openMSP430_uart.ucf
@@ -24,3 +24,10 @@ NET "ROT_A"             LOC = "J2"    | PULLDOWN;   # pin 03
 NET "ROT_B"             LOC = "K2"    | PULLDOWN;   # pin 05
 NET "ROT_PRESS"         LOC = "E4"    | PULLDOWN;   # pin 07
 
+#==============================================================================#
+# PWM output                                                                   #
+#==============================================================================#
+# Connected to the header J7 (LVDS TX STATUS).
+
+NET "PWM"               LOC = "C1";                 # pin 01
+