Peripheral connected to the quadcount module and an incremental encoder. Interrupt...

[fpga/virtex2/uart.git] / software / hardware.h

diff --git a/software/hardware.h b/software/hardware.h
index a586ac350c1bf51d0fdb98e61444fe3c50699f45..cb99613037ab0d9a84607955a4aee5915b01a707 100644 (file)
--- a/software/hardware.h
+++ b/software/hardware.h
@@ -9,6 +9,15 @@
 #include <iomacros.h>
 
 
+//QuadCounter registers
+#define QCNTL_             0x0150
+sfrw(QCNTL,QCNTL_);
+#define QCNTH_             0x0152
+sfrw(QCNTH,QCNTH_);
+//QuadCount IRQ vector
+#define QCNT_VECTOR        14
+
+
 //PINS
 //PORT1
 #define TX              BIT1
@@ -57,9 +66,11 @@
 //#define BAUD           1042              //19200 @20.0MHz div 1
 //#define BAUD            521              //38400 @20.0MHz div 1
 //#define BAUD            347              //57600 @20.0MHz div 1
-#define BAUD            174              //115200 @20.0MHz div 1
+//#define BAUD            174              //115200 @20.0MHz div 1
 //#define BAUD             87              //230400 @20.0MHz div 1
 
+#define BAUD            208              //115200 @24.0MHz div 1
+
 //Selection of 'Digitally Controlled Oszillator' (desired frquency in HZ, 1..3 MHz)
 #define DCO_FREQ        1536000         //3072000/2 makes 9600 a bit more precise