+ Quadcount submodule

[fpga/virtex2/uart.git] / openMSP430_uart.vhd

diff --git a/openMSP430_uart.vhd b/openMSP430_uart.vhd
index f1fa1c2be895168d5b60521c7ddb4a80f95b4c3a..b6e3eceae7e709a5640399e47d2976b297d2245e 100644 (file)
--- a/openMSP430_uart.vhd
+++ b/openMSP430_uart.vhd
@@ -7,8 +7,9 @@ entity openMSP430_uart is
   port (
     CLK_24MHz: in std_logic;
     RESET: in std_logic;
-    DISPLAY1: out std_logic_vector(6 downto 0);
-    DISPLAY2: out std_logic_vector(6 downto 0)
+
+    RXD : out std_logic;
+    TXD : in std_logic
   );
 end openMSP430_uart;
 
@@ -118,9 +119,47 @@ architecture rtl of openMSP430_uart is
     );
   end component;
 
+  component omsp_timerA
+    port (
+      irq_ta0     : out std_logic;      -- Timer A interrupt: TACCR0
+      irq_ta1     : out std_logic;                       -- Timer A interrupt: TAIV, TACCR1, TACCR2
+      per_dout    : out std_logic_vector (15 downto 0);  -- Peripheral data output
+      ta_out0     : out std_logic;                       -- Timer A output 0
+      ta_out0_en  : out std_logic;      -- Timer A output 0 enable
+      ta_out1     : out std_logic;      -- Timer A output 1
+      ta_out1_en  : out std_logic;      -- Timer A output 1 enable
+      ta_out2     : out std_logic;      -- Timer A output 2
+      ta_out2_en  : out std_logic;      -- Timer A output 2 enable
+
+      aclk_en     : in std_logic;       -- ACLK enable (from CPU)
+      dbg_freeze  : in std_logic;       -- Freeze Timer A counter
+      inclk       : in std_logic;       -- INCLK external timer clock (SLOW)
+      irq_ta0_acc : in std_logic;       -- Interrupt request TACCR0 accepted
+      mclk        : in std_logic;                        -- Main system clock
+      per_addr    : in std_logic_vector (7  downto 0);   -- Peripheral address
+      per_din     : in std_logic_Vector (15 downto 0);   -- Peripheral data input
+      per_en      : in std_logic;                        -- Peripheral enable (high active)
+      per_wen     : in std_logic_vector (1  downto 0);   -- Peripheral write enable (high active)
+      puc         : in std_logic;                        -- Main system reset
+      smclk_en    : in std_logic;       -- SMCLK enable (from CPU)
+      ta_cci0a    : in std_logic;       -- Timer A capture 0 input A
+      ta_cci0b    : in std_logic;       -- Timer A capture 0 input B
+      ta_cci1a    : in std_logic;       -- Timer A capture 1 input A
+      ta_cci1b    : in std_logic;       -- Timer A capture 1 input B
+      ta_cci2a    : in std_logic;       -- Timer A capture 2 input A
+      ta_cci2b    : in std_logic;       -- Timer A capture 2 input B
+      taclk       : in std_logic        -- TACLK external timer clock (SLOW)
+    );
+  end component;
+
 
   signal mclk : std_logic;
   signal puc : std_logic;
+  signal aclk_en : std_logic;
+  signal smclk_en : std_logic;
+  
+  signal irq_acc : std_logic_vector (13 downto 0);
+  signal irq : std_logic_vector (13 downto 0);
 
   signal pmem_addr : std_logic_vector (10 downto 0);
   signal pmem_dout : std_logic_vector (15 downto 0);
@@ -138,18 +177,25 @@ architecture rtl of openMSP430_uart is
   signal per_en : std_logic;
   signal per_addr : std_logic_vector (7 downto 0);
 
+
+  signal gpio_per_dout : std_logic_vector (15 downto 0);
+  signal timerA_per_dout : std_logic_vector (15 downto 0);
+
+  signal irq_ta0 : std_logic;
+  signal irq_ta1 : std_logic;
+
 --------------------------------------------------------------------------------
 
 begin
   openMSP430_0 : openMSP430 port map (
-    aclk_en       => open,
+    aclk_en       => aclk_en,
     dbg_freeze    => open,
     dbg_uart_txd  => open,
     dmem_addr     => dmem_addr,
     dmem_cen      => dmem_cen,
     dmem_din      => dmem_din,
     dmem_wen      => dmem_wen,
-    irq_acc       => open,
+    irq_acc       => irq_acc,
     mclk          => mclk,
     per_addr      => per_addr,
     per_din       => per_din,
@@ -160,12 +206,12 @@ begin
     pmem_din      => open,
     pmem_wen      => open,
     puc           => puc,
-    smclk_en      => open,
+    smclk_en      => smclk_en,
   
     dbg_uart_rxd  => '0',
     dco_clk       => CLK_24MHz,
     dmem_dout     => dmem_dout,
-    irq           => (others => '0'),
+    irq           => irq,
     lfxt_clk      => '0',
     nmi           => '0',
     per_dout      => per_dout,
@@ -222,12 +268,12 @@ begin
     port map (
       irq_port1 => open,
       irq_port2 => open,
-      p1_dout (6 downto 0) => DISPLAY1,
-      p1_dout (7) => open,
+      p1_dout (7 downto 2) => open,
+      p1_dout (1) => RXD,
+      p1_dout (0) => open,
       p1_dout_en => open,
       p1_sel => open,
-      p2_dout (6 downto 0) => DISPLAY2,
-      p2_dout (7) => open,
+      p2_dout => open,
       p2_dout_en => open,
       p2_sel => open,
       p3_dout => open,
@@ -242,7 +288,7 @@ begin
       p6_dout => open,
       p6_dout_en => open,
       p6_sel => open,
-      per_dout => per_dout,
+      per_dout => gpio_per_dout,
       mclk => mclk,
       p1_din => (others => '0'),
       p2_din => (others => '0'),
@@ -257,6 +303,44 @@ begin
       puc => puc
     );
 
+  omsp_timerA_0 : omsp_timerA port map (
+    irq_ta0     => irq_ta0,
+    irq_ta1     => irq_ta1,
+    per_dout    => timerA_per_dout,
+    ta_out0     => open,
+    ta_out0_en  => open,
+    ta_out1     => open,
+    ta_out1_en  => open,
+    ta_out2     => open,
+    ta_out2_en  => open,
+
+    aclk_en     => aclk_en,
+    dbg_freeze  => '0',
+    inclk       => '0',
+    irq_ta0_acc => irq_acc (9),
+    mclk        => mclk,
+    per_addr    => per_addr,
+    per_din     => per_din,
+    per_en      => per_en,
+    per_wen     => per_wen,
+    puc         => puc,
+    smclk_en    => smclk_en,
+    ta_cci0a    => '0',
+    ta_cci0b    => TXD,
+    ta_cci1a    => '0',
+    ta_cci1b    => '0',
+    ta_cci2a    => '0',
+    ta_cci2b    => '0',
+    taclk       => '0'
+  );
+
+--------------------------------------------------------------------------------
+
+  per_dout <=  gpio_per_dout or timerA_per_dout;
+  
+  irq <= (9 => irq_ta0,
+          8 => irq_ta1,
+          others => '0');
   
 end rtl;