--- /dev/null
+The following files were generated for 'rom_8x2k' in directory
+coregen/:
+
+rom_8x2k_xmdf.tcl:
+ Please see the core data sheet.
+
+rom_8x2k_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+rom_8x2k.sym:
+ Please see the core data sheet.
+
+rom_8x2k.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+rom_8x2k.vho:
+ VHO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a VHDL design.
+
+rom_8x2k_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+rom_8x2k.asy:
+ Graphical symbol information file. Used by the ISE tools and some
+ third party tools to create a symbol representing the core.
+
+rom_8x2k.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+rom_8x2k.vhd:
+ VHDL wrapper file provided to support functional simulation. This
+ file contains simulation model customization data that is passed to
+ a parameterized simulation model for the core.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+