Added top-module.

[fpga/virtex2/plasma.git] / top_plasma.vhd

diff --git a/top_plasma.vhd b/top_plasma.vhd
new file mode 100644 (file)
index 0000000..17dee5c
--- /dev/null
+++ b/top_plasma.vhd
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+entity top_plasma is
+  port (
+    CLK_24MHz : in  std_logic;
+    RESET_N   : in  std_logic;
+    RXD       : in  std_logic;
+    TXD       : out std_logic);
+end entity top_plasma;
+
+--------------------------------------------------------------------------------
+
+architecture compose of top_plasma is
+
+  signal clk   : std_logic;
+  signal reset : std_logic;
+  
+begin
+
+  clk   <= CLK_24MHz;
+  reset <= not RESET_N;
+  
+  
+  plasma_1: entity work.plasma
+    generic map (
+      memory_type => "XILINX_16X",
+      log_file    => "UNUSED",
+      ethernet    => '0',
+      use_cache   => '0')
+    port map (
+      clk          => clk,
+      reset        => reset,
+      uart_write   => TXD,
+      uart_read    => RXD,
+      address      => open,
+      byte_we      => open,
+      data_write   => open,
+      data_read    => (others => '0'),
+      mem_pause_in => '0',
+      no_ddr_start => open,
+      no_ddr_stop  => open,
+      gpio0_out    => open,
+      gpioA_in     => (others => '0'));
+  
+
+end architecture compose;
+