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(parent: c4b724c) | patch
Added top-module.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Mon, 14 Feb 2011 19:24:15 +0000 (20:24 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Mon, 14 Feb 2011 19:24:15 +0000 (20:24 +0100)
commit0e39c3079f3bd0c4f9ba6b71e9b2cc136d90d8a1
treebb14f9a83f350f08114ec82dbc9ed73965fde54btree | snapshot
parentc4b724cce9e972b86a4bac2c308e50d57a06ee24commit | diff
Added top-module.

Only reset, clock (24MHz) and rs-232 TXD, RXD signals are conected.
build/Makefile diff | blob | history
top_plasma.prj diff | blob | history
top_plasma.ucf [new file with mode: 0644] blob
top_plasma.vhd [new file with mode: 0644] blob
Plasma - most MIPS I - test top level design for Virtex 2 V2MB1000 board