Added top-module.

[fpga/virtex2/plasma.git] / top_plasma.ucf

diff --git a/top_plasma.ucf b/top_plasma.ucf
new file mode 100644 (file)
index 0000000..f33685d
--- /dev/null
+++ b/top_plasma.ucf
@@ -0,0 +1,16 @@
+#==============================================================================#
+# Clock & Reset                                                                #
+#==============================================================================#
+
+NET "CLK_24MHz"         LOC = "A11" |     PERIOD =  41.7 ns LOW  20.9 ns;
+
+NET "RESET_N"           LOC = "B6";
+
+
+#==============================================================================#
+# RS-232 Port                                                                  #
+#==============================================================================#
+
+NET "TXD"               LOC = "A7";     # output from the board (from FPGA)
+NET "RXD"               LOC = "B7";     # input to the board (to FPGA)
+