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Improper top module signals initialization.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 20:46:03 +0000 (22:46 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 21:41:04 +0000 (23:41 +0200)

No differences found
MSP430 BLDC control HW and PXMC SW - top level design for Virtex 2 V2MB1000 board