2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
5 --------------------------------------------------------------------------------
9 W : integer := 8); -- GPIO port width (pin count)
11 -- Peripheral bus interface
12 ACK_O : out std_logic;
13 ADR_I : in std_logic_vector (1 downto 0);
15 DAT_I : in std_logic_vector (W-1 downto 0);
16 DAT_O : out std_logic_vector (W-1 downto 0);
22 GPIO_I : in std_logic_vector (W-1 downto 0);
23 GPIO_O : out std_logic_vector (W-1 downto 0));
26 --------------------------------------------------------------------------------
28 architecture behavioral of gpio is
30 signal gpio_output : std_logic_vector (W-1 downto 0) := (others => '0');
31 signal gpio_output_new : std_logic_vector (W-1 downto 0);
32 signal write_en : std_logic;
36 ACK_O <= SEL_I and STB_I;
41 gpio_output when "01",
42 (others => '-') when others;
48 gpio_output or DAT_I when "10",
49 gpio_output and not DAT_I when "11",
50 gpio_output when others;
52 write_en <= SEL_I and STB_I and WE_I;
54 process (CLK_I, RST_I) is
56 if rising_edge(CLK_I) then
58 gpio_output <= (others => '0');
60 if write_en = '1' then
61 gpio_output <= gpio_output_new;