1 #==============================================================================#
3 #==============================================================================#
6 NET "CLK_24MHz" LOC = "A11" | PERIOD = 41.7 ns LOW 20.9 ns;
7 NET "RESET" LOC = "B6";
10 #==============================================================================#
12 #==============================================================================#
14 NET "TXD" LOC = "A7"; # output from the board (from FPGA)
15 NET "RXD" LOC = "B7"; # input to the board (to FPGA)
18 #==============================================================================#
20 #==============================================================================#
21 # LEDs are connected to the ground
23 NET "LED0" LOC = "E10"; # Display2<5>
24 NET "LED1" LOC = "A8"; # Display2<1>
25 NET "LED2" LOC = "E7"; # Display2<3>
28 #==============================================================================#
30 #==============================================================================#
31 # This board with 3-phase power outputs and converters of hall and IRC
32 # signals is connected to the J4 header (LVDS TRANSMIT).
34 NET "PWM0" LOC = "F4" | IOSTANDARD = "LVCMOS33";
35 NET "PWM0_EN" LOC = "F3" | IOSTANDARD = "LVCMOS33";
36 NET "PWM1" LOC = "G4" | IOSTANDARD = "LVCMOS33";
37 NET "PWM1_EN" LOC = "G3" | IOSTANDARD = "LVCMOS33";
38 NET "PWM2" LOC = "H4" | IOSTANDARD = "LVCMOS33";
39 NET "PWM2_EN" LOC = "H3" | IOSTANDARD = "LVCMOS33";
41 NET "IRC_INDEX" LOC = "J4" | IOSTANDARD = "LVCMOS33";
42 NET "IRC_A" LOC = "J3" | IOSTANDARD = "LVCMOS33";
43 NET "IRC_B" LOC = "K4" | IOSTANDARD = "LVCMOS33";
45 NET "HAL0" LOC = "J5" | IOSTANDARD = "LVCMOS33";
46 NET "HAL1" LOC = "K5" | IOSTANDARD = "LVCMOS33";
47 NET "HAL2" LOC = "K6" | IOSTANDARD = "LVCMOS33";