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+ Top level design
[fpga/virtex2/blink.git] / memory.bmm
1 //ADDRESS_SPACE blockrom RAMB16 [0xfc00:0xffff]
2 ADDRESS_SPACE blockrom RAMB16 [0xf000:0xffff]
3
4   BUS_BLOCK
5
6       rom_8x2k_lo/B8 [7:0];
7       rom_8x2k_hi/B8 [15:8];
8
9   END_BUS_BLOCK;
10
11 END_ADDRESS_SPACE;
12
13 ADDRESS_SPACE blockram RAMB16 [0x0200:0x11ff]
14
15   BUS_BLOCK
16
17       ram_8x512_lo/B8 [7:0];
18       ram_8x512_hi/B8 [15:8];
19
20   END_BUS_BLOCK;
21
22 END_ADDRESS_SPACE;