First prototype of receiver shift register.

[fpga/uart.git] / uart.vhd

diff --git a/uart.vhd b/uart.vhd
index fe5714f31833c5d9917e7b056c34c823d009067f..a5999089a11135173158276724b9db9ee5b7e5f8 100644 (file)
--- a/uart.vhd
+++ b/uart.vhd
@@ -75,6 +75,7 @@ architecture dataflow of uart is
       reset    : in  std_logic;
       we       : in  std_logic;
       re       : in  std_logic;
+      clear_ow : in  std_logic;
       d_in     : in  std_logic_vector (7 downto 0);
       d_out    : out std_logic_vector (7 downto 0);
       full     : out std_logic;
@@ -160,6 +161,7 @@ begin
     reset    => puc,
     we       => tx_fifo_we,
     re       => tx_fifo_re,
+    clear_ow => '0',
     d_in     => per_din (7 downto 0),
     d_out    => tx_data,
     full     => open,