Wave_table initialization data format modified.

[fpga/pwm.git] / vector_gen.vhd

diff --git a/vector_gen.vhd b/vector_gen.vhd
index f32890bd4194ec9f3684893d958d4ba03bfbdda0..a58d255b3d0fb7f89dc95da512ec2c93274ff6ca 100644 (file)
--- a/vector_gen.vhd
+++ b/vector_gen.vhd
@@ -30,7 +30,7 @@ entity vector_gen is
     IRF_CYC_O : out std_logic;
     IRF_DAT_I : in  std_logic_vector (15 downto 0);
     IRF_DAT_O : out std_logic_vector (15 downto 0);
-    IRF_STB_O : out std_logic;
+    IRF_STB_O : out std_logic := '0';
     IRF_WE_O  : out std_logic;
     -- Master interface to the wave look-up-table
     LUT_ADR_O : out std_logic_vector (LUT_ADR_W-1 downto 0);
@@ -51,9 +51,9 @@ architecture behavioral of vector_gen is
   constant P2_ADR : irf_adr_t := conv_std_logic_vector(P_BASE+P2_OFF, IRF_ADR_W);
   constant P3_ADR : irf_adr_t := conv_std_logic_vector(P_BASE+P3_OFF, IRF_ADR_W);
 
-  signal state     : state_t;
+  signal state     : state_t := ready;
   signal angle_in  : lut_adr_t;
-  signal ack_latch : std_logic;
+  signal ack_latch : std_logic := '0';
 
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