library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------------------------------

entity vector_gen is
  generic (
    LUT_DAT_W  : integer := 10;
    LUT_ADR_W  : integer := 9;
    LUT_P1_OFF : integer := 0;
    LUT_P2_OFF : integer := 171;
    LUT_P3_OFF : integer := 341;
    IRF_ADR_W  : integer := 5;
    A_BASE     : integer := 0;
    P_BASE     : integer := 1;
    P1_OFF     : integer := 0;
    P2_OFF     : integer := 1;
    P3_OFF     : integer := 2);
  port (
    -- Primary slave interface
    ACK_O     : out std_logic;
    CLK_I     : in  std_logic;
    RST_I     : in  std_logic;
    STB_I     : in  std_logic;
    -- Master interface to the interface memory
    IRF_ACK_I : in  std_logic;
    IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
    IRF_CYC_O : out std_logic;
    IRF_DAT_I : in  std_logic_vector (15 downto 0);
    IRF_DAT_O : out std_logic_vector (15 downto 0);
    IRF_STB_O : out std_logic := '0';
    IRF_WE_O  : out std_logic;
    -- Master interface to the wave look-up-table
    LUT_ADR_O : out std_logic_vector (LUT_ADR_W-1 downto 0);
    LUT_DAT_I : in  std_logic_vector (LUT_DAT_W-1 downto 0);
    LUT_STB_O : out std_logic);
end entity vector_gen;

--------------------------------------------------------------------------------

architecture behavioral of vector_gen is

  type state_t is (ready, angle, phase1, phase2, phase3, done);
  subtype irf_adr_t is std_logic_vector (IRF_ADR_W-1 downto 0);
  subtype lut_adr_t is std_logic_vector (LUT_ADR_W-1 downto 0);

  constant A_ADR  : irf_adr_t := conv_std_logic_vector(A_BASE, IRF_ADR_W);
  constant P1_ADR : irf_adr_t := conv_std_logic_vector(P_BASE+P1_OFF, IRF_ADR_W);
  constant P2_ADR : irf_adr_t := conv_std_logic_vector(P_BASE+P2_OFF, IRF_ADR_W);
  constant P3_ADR : irf_adr_t := conv_std_logic_vector(P_BASE+P3_OFF, IRF_ADR_W);

  signal state     : state_t := ready;
  signal angle_in  : lut_adr_t;
  signal ack_latch : std_logic := '0';

--------------------------------------------------------------------------------
  
begin

  IRF_DAT_O (IRF_DAT_O'HIGH downto LUT_DAT_I'HIGH+1) <= (others => '0');
  IRF_DAT_O (LUT_DAT_I'RANGE) <= LUT_DAT_I;
  
  ACK_O <= ack_latch and STB_I;

  
  FSM : process (CLK_I) is
  begin
    if rising_edge(CLK_I) then
      if RST_I = '1' or STB_I = '0' then
        state     <= ready;
        ack_latch <= '0';
        IRF_CYC_O <= '0';
        IRF_STB_O <= '0';
        IRF_WE_O  <= '0';
        LUT_STB_O <= '0';

      else
        case state is
          when ready =>
            if STB_I = '1' then
              state     <= angle;
              IRF_ADR_O <= A_ADR;
              IRF_CYC_O <= '1';
              IRF_STB_O <= '1';
            end if;

          when angle =>
            if IRF_ACK_I = '1' then
              state     <= phase1;
              angle_in  <= IRF_DAT_I(angle_in'RANGE);
              LUT_ADR_O <= IRF_DAT_I(angle_in'RANGE) + LUT_P1_OFF;
              LUT_STB_O <= '1';
            end if;
            
          when phase1 =>
            state     <= phase2;
            IRF_ADR_O <= P1_ADR;
            IRF_WE_O  <= '1';
            LUT_ADR_O <= angle_in + LUT_P2_OFF;
            
          when phase2 =>
            state     <= phase3;
            IRF_ADR_O <= P2_ADR;
            LUT_ADR_O <= angle_in + LUT_P3_OFF;

          when phase3 =>
            state     <= done;
            IRF_ADR_O <= P3_ADR;

            
          when done =>
            ack_latch <= '1';
            IRF_CYC_O <= '0';
            IRF_STB_O <= '0';
            IRF_WE_O  <= '0';
            LUT_STB_O <= '0';
        end case;

      end if;
    end if;
  end process;

end architecture behavioral;