2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
6 --------------------------------------------------------------------------------
10 LUT_ADR_W : integer := 10;
11 LUT_DAT_W : integer := 9;
12 IRF_ADR_W : integer := 5);
14 -- Primary slave intefrace
15 ACK_O : out std_logic;
19 -- Wave table interface
20 LUT_STB_O : out std_logic;
21 LUT_ADR_O : out std_logic_vector (LUT_ADR_W-1 downto 0);
22 LUT_DAT_I : in std_logic_vector (LUT_DAT_W-1 downto 0);
24 IRC_DAT_I : in std_logic_vector (15 downto 0);
26 PWM_DAT_O : out std_logic_vector (LUT_DAT_W-1 downto 0);
27 PWM1_STB_O : out std_logic;
28 PWM2_STB_O : out std_logic;
29 PWM3_STB_O : out std_logic;
30 -- Shared memory interface
31 IRF_ACK_I : in std_logic;
32 IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
33 IRF_DAT_I : in std_logic_vector (15 downto 0);
34 IRF_DAT_O : out std_logic_vector (15 downto 0);
35 IRF_STB_O : out std_logic;
36 IRF_WE_O : out std_logic);
39 --------------------------------------------------------------------------------
41 architecture behavioral of mcc is
43 constant MCC_W : integer := 5;
44 constant MUX_W : integer := 2;
47 signal MCC_ACK : std_logic_vector (MCC_W-1 downto 0);
48 signal MCC_STB : std_logic_vector (MCC_W-1 downto 0);
49 signal MCC_MUX_CODE : std_logic_vector (MUX_W-1 downto 0);
50 signal MCC_MUX_EN : std_logic;
52 signal MASTER_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
53 signal MASTER_IRF_DAT_O : std_logic_vector (15 downto 0);
54 signal MASTER_IRF_STB_O : std_logic;
55 signal MASTER_IRF_WE_O : std_logic;
57 signal VECTOR_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
58 signal VECTOR_IRF_DAT_O : std_logic_vector (15 downto 0);
59 signal VECTOR_IRF_STB_O : std_logic;
60 signal VECTOR_IRF_WE_O : std_logic;
63 type state_t is (ready, read_mask, do_mcc, done);
65 signal state : state_t;
67 signal mcc_mask : std_logic_vector (MCC_W-1 downto 0);
68 signal mcc_ack_inner : std_logic_vector (MCC_W downto 0);
69 signal mcc_stb_inner : std_logic_vector (MCC_W-1 downto 0);
70 signal mux_code_inner : std_logic_vector (MUX_W-1 downto 0);
71 signal mcc_exec : std_logic;
73 --------------------------------------------------------------------------------
77 IRF_ADR_O <= MASTER_IRF_ADR_O when MCC_MUX_EN = '0' else
78 VECTOR_IRF_ADR_O when MCC_MUX_CODE = 1 else
81 IRF_DAT_O <= MASTER_IRF_DAT_O when MCC_MUX_EN = '0' else
82 VECTOR_IRF_DAT_O when MCC_MUX_CODE = 1 else
85 IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else
86 VECTOR_IRF_STB_O when MCC_MUX_CODE = 1 else
89 IRF_WE_O <= MASTER_IRF_WE_O when MCC_MUX_EN = '0' else
90 VECTOR_IRF_WE_O when MCC_MUX_CODE = 1 else
94 mcc_master_1 : entity work.mcc_master
98 IRF_ADR_W => IRF_ADR_W)
104 MCC_STB_O => MCC_STB,
105 MCC_ACK_I => MCC_ACK,
106 MCC_MUX_CODE => MCC_MUX_CODE,
107 MCC_MUX_EN => MCC_MUX_EN,
108 IRF_ACK_I => IRF_ACK_I,
109 IRF_ADR_O => MASTER_IRF_ADR_O,
110 IRF_DAT_I => IRF_DAT_I,
111 IRF_DAT_O => MASTER_IRF_DAT_O,
112 IRF_STB_O => MASTER_IRF_STB_O,
113 IRF_WE_O => MASTER_IRF_WE_O);
115 vector_gen_1 : entity work.vector_gen
120 ACK_O => MCC_ACK (1),
123 STB_I => MCC_STB (1),
124 IRF_ACK_I => IRF_ACK_I,
125 IRF_ADR_O => VECTOR_IRF_ADR_O,
127 IRF_DAT_I => IRF_DAT_I,
128 IRF_DAT_O => VECTOR_IRF_DAT_O,
129 IRF_STB_O => VECTOR_IRF_STB_O,
130 IRF_WE_O => VECTOR_IRF_WE_O,
131 LUT_ADR_O => LUT_ADR_O,
132 LUT_DAT_I => LUT_DAT_I,
133 LUT_STB_O => LUT_STB_O);
135 end architecture behavioral;