2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
6 --------------------------------------------------------------------------------
10 LUT_ADR_W : integer := 10;
11 LUT_DAT_W : integer := 9);
13 -- Primary slave intefrace
14 ACK_O : out std_logic;
18 -- Wave table interface
19 LUT_STB_O : out std_logic;
20 LUT_ADR_O : out std_logic_vector (LUT_ADR_W-1 downto 0);
21 LUT_DAT_I : in std_logic_vector (LUT_DAT_W-1 downto 0);
23 IRC_DAT_I : in std_logic_vector (15 downto 0);
25 PWM_DAT_O : out std_logic_vector (LUT_DAT_W-1 downto 0);
26 PWM1_STB_O : out std_logic;
27 PWM2_STB_O : out std_logic;
28 PWM3_STB_O : out std_logic;
29 -- Shared memory interface
30 IRF_ACK_I : in std_logic;
31 IRF_ADR_O : out std_logic_vector (4 downto 0);
32 IRF_DAT_I : in std_logic_vector (15 downto 0);
33 IRF_DAT_O : out std_logic_vector (15 downto 0);
34 IRF_STB_O : out std_logic;
35 IRF_WE_O : out std_logic);
38 --------------------------------------------------------------------------------
40 architecture behavioral of mcc is
42 constant IRF_ADR_W : integer := 5;
44 constant MCC_W : integer := 6;
45 constant MUX_W : integer := 3;
47 constant P_BASE : integer := 16;
48 constant P_SIZE : integer := 4;
51 signal MCC_ACK : std_logic_vector (MCC_W-1 downto 0);
52 signal MCC_STB : std_logic_vector (MCC_W-1 downto 0);
53 signal MCC_MUX_CODE : std_logic_vector (MUX_W-1 downto 0);
54 signal MCC_MUX_EN : std_logic;
56 signal MUL_A : std_logic_vector (15 downto 0);
57 signal MUL_B : std_logic_vector (15 downto 0);
58 signal MUL_PROD : std_logic_vector (31 downto 0);
60 signal MASTER_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
61 signal MASTER_IRF_DAT_O : std_logic_vector (15 downto 0);
62 signal MASTER_IRF_STB_O : std_logic;
63 signal MASTER_IRF_WE_O : std_logic;
65 signal VECTOR_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
66 signal VECTOR_IRF_DAT_O : std_logic_vector (15 downto 0);
67 signal VECTOR_IRF_STB_O : std_logic;
68 signal VECTOR_IRF_WE_O : std_logic;
70 signal SCALE_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
71 signal SCALE_IRF_DAT_O : std_logic_vector (15 downto 0);
72 signal SCALE_IRF_STB_O : std_logic;
73 signal SCALE_IRF_WE_O : std_logic;
74 signal SCALE_SL_ACK_O : std_logic;
75 signal SCALE_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
76 signal SCALE_SL_STB_I : std_logic;
78 signal PMIN_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
79 signal PMIN_IRF_DAT_O : std_logic_vector (15 downto 0);
80 signal PMIN_IRF_STB_O : std_logic;
81 signal PMIN_IRF_WE_O : std_logic;
83 signal PWM_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
84 signal PWM_IRF_STB_O : std_logic;
85 --signal PWM_DAT_O : std_logic_vector (LUT_DAT_W-1 downto 0);
86 signal PWM_STB_O : std_logic;
87 signal PWM_SL_ACK_O : std_logic;
88 signal PWM_SL_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
89 signal PWM_SL_STB_I : std_logic;
90 signal PWM_SL_MUX_CODE : std_logic_vector (1 downto 0);
92 signal IRC_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
93 signal IRC_IRF_DAT_O : std_logic_vector (15 downto 0);
94 signal IRC_IRF_STB_O : std_logic;
95 signal IRC_IRF_WE_O : std_logic;
97 signal BASE_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
98 signal BASE_IRF_DAT_O : std_logic_vector (15 downto 0);
99 signal BASE_IRF_STB_O : std_logic;
100 signal BASE_IRF_WE_O : std_logic;
103 type state_t is (ready, read_mask, do_mcc, done);
105 signal state : state_t;
107 signal mcc_mask : std_logic_vector (MCC_W-1 downto 0);
108 signal mcc_ack_inner : std_logic_vector (MCC_W downto 0);
109 signal mcc_stb_inner : std_logic_vector (MCC_W-1 downto 0);
110 signal mux_code_inner : std_logic_vector (MUX_W-1 downto 0);
111 signal mcc_exec : std_logic;
113 --------------------------------------------------------------------------------
117 IRF_ADR_O <= MASTER_IRF_ADR_O when MCC_MUX_EN = '0' else
118 IRC_IRF_ADR_O when MCC_MUX_CODE = 0 else
119 BASE_IRF_ADR_O when MCC_MUX_CODE = 1 else
120 VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else
121 SCALE_IRF_ADR_O when MCC_MUX_CODE = 3 else
122 PMIN_IRF_ADR_O when MCC_MUX_CODE = 4 else
123 PWM_IRF_ADR_O when MCC_MUX_CODE = 5 else
126 IRF_DAT_O <= MASTER_IRF_DAT_O when MCC_MUX_EN = '0' else
127 IRC_IRF_DAT_O when MCC_MUX_CODE = 0 else
128 BASE_IRF_DAT_O when MCC_MUX_CODE = 1 else
129 VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else
130 SCALE_IRF_DAT_O when MCC_MUX_CODE = 3 else
131 PMIN_IRF_DAT_O when MCC_MUX_CODE = 4 else
134 IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else
135 IRC_IRF_STB_O when MCC_MUX_CODE = 0 else
136 BASE_IRF_STB_O when MCC_MUX_CODE = 1 else
137 VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else
138 SCALE_IRF_STB_O when MCC_MUX_CODE = 3 else
139 PMIN_IRF_STB_O when MCC_MUX_CODE = 4 else
140 PWM_IRF_STB_O when MCC_MUX_CODE = 5 else
143 IRF_WE_O <= MASTER_IRF_WE_O when MCC_MUX_EN = '0' else
144 IRC_IRF_WE_O when MCC_MUX_CODE = 0 else
145 BASE_IRF_WE_O when MCC_MUX_CODE = 1 else
146 VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else
147 SCALE_IRF_WE_O when MCC_MUX_CODE = 3 else
148 PMIN_IRF_WE_O when MCC_MUX_CODE = 4 else
152 PWM1_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 0 else '0';
153 PWM2_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 1 else '0';
154 PWM3_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 2 else '0';
158 mcc_master_1 : entity work.mcc_master
162 IRF_ADR_W => IRF_ADR_W)
168 MCC_STB_O => MCC_STB,
169 MCC_ACK_I => MCC_ACK,
170 MCC_MUX_CODE => MCC_MUX_CODE,
171 MCC_MUX_EN => MCC_MUX_EN,
172 IRF_ACK_I => IRF_ACK_I,
173 IRF_ADR_O => MASTER_IRF_ADR_O,
174 IRF_DAT_I => IRF_DAT_I,
175 IRF_DAT_O => MASTER_IRF_DAT_O,
176 IRF_STB_O => MASTER_IRF_STB_O,
177 IRF_WE_O => MASTER_IRF_WE_O);
179 multiplier_1 : entity work.multiplier
185 irc_dump_1 : entity work.irc_dump
187 IRF_ADR_W => IRF_ADR_W,
190 ACK_O => MCC_ACK (0),
193 STB_I => MCC_STB (0),
194 IRC_DAT_I => IRC_DAT_I,
195 IRF_ACK_I => IRF_ACK_I,
196 IRF_ADR_O => IRC_IRF_ADR_O,
197 IRF_DAT_O => IRC_IRF_DAT_O,
198 IRF_STB_O => IRC_IRF_STB_O,
199 IRF_WE_O => IRC_IRF_WE_O);
201 irc_base_1 : entity work.irc_base
203 IRF_ADR_W => IRF_ADR_W,
210 ACK_O => MCC_ACK (1),
213 STB_I => MCC_STB (1),
214 IRF_ACK_I => IRF_ACK_I,
215 IRF_ADR_O => BASE_IRF_ADR_O,
216 IRF_DAT_I => IRF_DAT_I,
217 IRF_DAT_O => BASE_IRF_DAT_O,
218 IRF_STB_O => BASE_IRF_STB_O,
219 IRF_WE_O => BASE_IRF_WE_O,
222 vector_gen_1 : entity work.vector_gen
236 ACK_O => MCC_ACK (2),
239 STB_I => MCC_STB (2),
240 IRF_ACK_I => IRF_ACK_I,
241 IRF_ADR_O => VECTOR_IRF_ADR_O,
243 IRF_DAT_I => IRF_DAT_I,
244 IRF_DAT_O => VECTOR_IRF_DAT_O,
245 IRF_STB_O => VECTOR_IRF_STB_O,
246 IRF_WE_O => VECTOR_IRF_WE_O,
247 LUT_ADR_O => LUT_ADR_O,
248 LUT_DAT_I => LUT_DAT_I,
249 LUT_STB_O => LUT_STB_O);
251 vector_scale_sequencer : entity work.sequencer
253 IRF_ADR_W => IRF_ADR_W,
257 ACK_O => MCC_ACK (3),
260 STB_I => MCC_STB (3),
261 IRF_ADR_O => SCALE_IRF_ADR_O,
262 SL_ACK_I => SCALE_SL_ACK_O,
263 SL_IRF_ADR_I => SCALE_SL_IRF_ADR_O,
264 SL_STB_O => SCALE_SL_STB_I,
265 SL_MUX_CODE => open);
267 vector_scale_1 : entity work.vector_scale
269 IRF_ADR_W => IRF_ADR_W,
272 PHASE_BASE => P_BASE,
275 VECTOR_W => LUT_DAT_W)
277 ACK_O => SCALE_SL_ACK_O,
280 STB_I => SCALE_SL_STB_I,
283 MUL_PROD => MUL_PROD,
284 IRF_ACK_I => IRF_ACK_I,
285 IRF_ADR_O => SCALE_SL_IRF_ADR_O,
286 IRF_DAT_I => IRF_DAT_I,
287 IRF_DAT_O => SCALE_IRF_DAT_O,
288 IRF_STB_O => SCALE_IRF_STB_O,
289 IRF_WE_O => SCALE_IRF_WE_O);
291 pwm_min_1 : entity work.pwm_min
293 IRF_ADR_W => IRF_ADR_W,
301 ACK_O => MCC_ACK (4),
304 STB_I => MCC_STB (4),
305 IRF_ACK_I => IRF_ACK_I,
306 IRF_ADR_O => PMIN_IRF_ADR_O,
307 IRF_DAT_I => IRF_DAT_I,
308 IRF_DAT_O => PMIN_IRF_DAT_O,
309 IRF_STB_O => PMIN_IRF_STB_O,
310 IRF_WE_O => PMIN_IRF_WE_O);
312 pwm_dump_sequencer : entity work.sequencer
314 IRF_ADR_W => IRF_ADR_W,
318 ACK_O => MCC_ACK (5),
321 STB_I => MCC_STB (5),
322 IRF_ADR_O => PWM_IRF_ADR_O,
323 SL_ACK_I => PWM_SL_ACK_O,
324 SL_IRF_ADR_I => PWM_SL_IRF_ADR_O,
325 SL_STB_O => PWM_SL_STB_I,
326 SL_MUX_CODE => PWM_SL_MUX_CODE);
328 pwm_min_dump_1 : entity work.pwm_min_dump
330 IRF_ADR_W => IRF_ADR_W,
337 ACK_O => PWM_SL_ACK_O,
340 STB_I => PWM_SL_STB_I,
341 PWM_DAT_O => PWM_DAT_O,
342 PWM_STB_O => PWM_STB_O,
343 IRF_ACK_I => IRF_ACK_I,
344 IRF_ADR_O => PWM_SL_IRF_ADR_O,
345 IRF_DAT_I => IRF_DAT_I,
346 IRF_STB_O => PWM_IRF_STB_O);
348 end architecture behavioral;