2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
9 --------------------------------------------------------------------------------
10 -- Waveform Look Up Table
12 -- It's based on behavioral description of full synchronous RAM, so it should be
13 -- mapped into FPGA BRAM. Interface is Wishbone like. Data and address bus width
16 -- Table is initialized from file specified by 'INIT_FILE' parameter. This is a
17 -- text file which contains one value per line. Values are typed in binary
18 -- format. Sample file 'sin.lut' together with Matlab generation function
19 -- 'gen_lut_sin.m' is enclosed.
20 --------------------------------------------------------------------------------
24 DAT_W : integer := 10;
26 INIT_FILE : string := "sin.lut");
28 ACK_O : out std_logic;
29 ADR_I : in std_logic_vector (ADR_W-1 downto 0);
31 DAT_I : in std_logic_vector (DAT_W-1 downto 0);
32 DAT_O : out std_logic_vector (DAT_W-1 downto 0);
35 end entity wave_table;
37 --------------------------------------------------------------------------------
39 architecture behavioral of wave_table is
41 constant SIZE : integer := 2**ADR_W;
43 type wave_table_t is array (0 to SIZE-1) of bit_vector (DAT_W-1 downto 0);
46 impure function init_table_from_file (file_name : string) return wave_table_t is
47 file table_file : text open read_mode is file_name;
48 variable file_line : line;
49 variable table : wave_table_t;
51 for i in wave_table_t'range loop
52 readline(table_file, file_line);
54 if endfile(table_file) then
55 file_close(table_file);
56 file_open(table_file, file_name, read_mode);
58 readline(table_file, file_line);
61 read(file_line, table(i));
65 end function init_table_from_file;
68 signal ram : wave_table_t := init_table_from_file(INIT_FILE);
70 signal stb_delayed : std_logic;
72 --------------------------------------------------------------------------------
76 MEM : process (CLK_I) is
77 variable address : integer;
79 address := conv_integer(ADR_I);
81 if rising_edge(CLK_I) then
86 DAT_O <= to_stdLogicVector(ram(address));
88 ram(address) <= to_bitvector(DAT_I);
95 ACK_O <= STB_I and (stb_delayed or WE_I);
97 end architecture behavioral;