2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
7 entity openMSP430_8_32_mul is
9 -- Clocks and reset (low active)
10 dco_clk : in std_logic;
11 lfxt_clk : in std_logic;
12 reset_n : in std_logic;
16 -- Periphery interface
17 per_addr : out std_logic_vector (7 downto 0);
18 per_din : out std_logic_vector (15 downto 0);
19 per_dout : in std_logic_vector (15 downto 0);
20 per_wen : out std_logic_vector (1 downto 0);
21 per_en : out std_logic;
23 irq : in std_logic_vector (13 downto 0);
24 irq_acc : out std_logic_vector (13 downto 0);
25 aclk_en : out std_logic;
26 smclk_en : out std_logic;
29 end entity openMSP430_8_32_mul;
31 --------------------------------------------------------------------------------
33 architecture rtl of openMSP430_8_32_mul is
35 component openMSP430 is
37 aclk_en : out std_logic; -- ACLK enable
38 dbg_freeze : out std_logic; -- Freeze peripherals
39 dbg_uart_txd : out std_logic; -- Debug interface: UART TXD
40 dmem_addr : out std_logic_vector; -- Data Memory address
41 dmem_cen : out std_logic; -- Data Memory chip enable (low active)
42 dmem_din : out std_logic_vector (15 downto 0); -- Data Memory data input
43 dmem_wen : out std_logic_vector (1 downto 0); -- Data Memory write enable (low active)
44 irq_acc : out std_logic_vector (13 downto 0); -- Interrupt request accepted (one-hot signal)
45 mclk : out std_logic; -- Main system clock
46 per_addr : out std_logic_vector (7 downto 0); -- Peripheral address
47 per_din : out std_logic_vector (15 downto 0); -- Peripheral data input
48 per_wen : out std_logic_vector (1 downto 0); -- Peripheral write enable (high active)
49 per_en : out std_logic; -- Peripheral enable (high active)
50 pmem_addr : out std_logic_vector; -- Program Memory address
51 pmem_cen : out std_logic; -- Program Memory chip enable (low active)
52 pmem_din : out std_logic_vector (15 downto 0); -- Program Memory data input (optional)
53 pmem_wen : out std_logic_vector (1 downto 0); -- Program Memory write enable (low active) (optional)
54 puc : out std_logic; -- Main system reset
55 smclk_en : out std_logic; -- SMCLK enable
57 dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD
58 dco_clk : in std_logic; -- Fast oscillator (fast clock)
59 dmem_dout : in std_logic_vector (15 downto 0); -- Data Memory data output
60 irq : in std_logic_vector (13 downto 0); -- Maskable interrupts
61 lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz)
62 nmi : in std_logic; -- Non-maskable interrupt (asynchronous)
63 per_dout : in std_logic_vector (15 downto 0); -- Peripheral data output
64 pmem_dout : in std_logic_vector (15 downto 0); -- Program Memory data output
65 reset_n : in std_logic -- Reset Pin (low active)
71 signal dmem_addr : std_logic_vector (11 downto 0);
72 signal dmem_cen : std_logic;
73 signal dmem_din : std_logic_vector (15 downto 0);
74 signal dmem_dout : std_logic_vector (15 downto 0);
75 signal dmem_wen : std_logic_vector (1 downto 0);
77 signal pmem_addr : std_logic_vector (13 downto 0);
78 signal pmem_cen : std_logic;
79 signal pmem_din : std_logic_vector (15 downto 0);
80 signal pmem_dout : std_logic_vector (15 downto 0);
81 signal pmem_wen : std_logic_vector (1 downto 0);
83 -- Inner signals used to connect built in components
84 signal inner_mclk : std_logic;
85 signal inner_puc : std_logic;
87 signal inner_per_addr : std_logic_vector (7 downto 0);
88 signal inner_per_din : std_logic_vector (15 downto 0);
89 signal inner_per_dout : std_logic_vector (15 downto 0);
90 signal inner_per_wen : std_logic_vector (1 downto 0);
91 signal inner_per_en : std_logic;
93 signal inner_irq_acc : std_logic_vector (13 downto 0);
94 signal inner_irq : std_logic_vector (13 downto 0);
97 signal uart_dout : std_logic_vector (15 downto 0);
98 signal uart_irq : std_logic;
100 --------------------------------------------------------------------------------
105 openMSP430_0 : openMSP430
109 dbg_uart_txd => open,
110 dmem_addr => dmem_addr,
111 dmem_cen => dmem_cen,
112 dmem_din => dmem_din,
113 dmem_wen => dmem_wen,
114 irq_acc => inner_irq_acc,
116 per_addr => inner_per_addr,
117 per_din => inner_per_din,
118 per_wen => inner_per_wen,
119 per_en => inner_per_en,
120 pmem_addr => pmem_addr,
121 pmem_cen => pmem_cen,
125 smclk_en => smclk_en,
129 dmem_dout => dmem_dout,
131 lfxt_clk => lfxt_clk,
133 per_dout => inner_per_dout,
134 pmem_dout => pmem_dout,
139 d_ram_hi : entity work.ram_generic
141 BRAM_TYPE => "RAMB16_S4",
152 din => dmem_din (15 downto 8),
153 dout => dmem_dout (15 downto 8));
155 d_ram_lo : entity work.ram_generic
157 BRAM_TYPE => "RAMB16_S4",
168 din => dmem_din (7 downto 0),
169 dout => dmem_dout (7 downto 0));
172 p_ram_hi : entity work.ram_generic
174 BRAM_TYPE => "RAMB16_S2",
184 din => pmem_din (15 downto 8),
185 dout => pmem_dout (15 downto 8));
187 p_ram_lo : entity work.ram_generic
189 BRAM_TYPE => "RAMB16_S2",
198 din => pmem_din (7 downto 0),
199 dout => pmem_dout (7 downto 0));
203 uart_o : entity work.uart
206 per_addr => inner_per_addr,
207 per_din => inner_per_din,
208 per_en => inner_per_en,
209 per_wen => inner_per_wen,
213 per_dout => uart_dout,
217 --------------------------------------------------------------------------------
219 inner_per_dout <= uart_dout or per_dout;
222 --inner_irq (6) <= uart_irq;
224 irq_acc <= inner_irq_acc;
226 per_addr <= inner_per_addr;
227 per_din <= inner_per_din;
228 per_wen <= inner_per_wen;
229 per_en <= inner_per_en;