TUMBL firmware and gtkwave log setup which demonstrates xmem access bug.

Incorrect/excessive data are read at time 9125 ns and are written
to r4. The this value is stored in sin_res at time 9190 ns.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/hw/tb/firmware-for-xmem-bug/Makefile b/hw/tb/firmware-for-xmem-bug/Makefile
new file mode 100644 (file)
index 0000000..1d75790
--- /dev/null
+++ b/hw/tb/firmware-for-xmem-bug/Makefile
@@ -0,0 +1,91 @@
+#===============================================================================
+# Firmware
+
+OUT := _build
+BUILDDIR := _build
+
+MB_CROSS_COMPILE ?= mbtumbl-elf-
+TARGET_CC := $(MB_CROSS_COMPILE)gcc
+TARGET_LD := $(MB_CROSS_COMPILE)ld
+TARGET_OBJCOPY := $(MB_CROSS_COMPILE)objcopy
+TARGET_OBJDUMP := $(MB_CROSS_COMPILE)objdump
+
+C_OBJS := $(OUT)/firmware.o
+A_OBJS :=
+CFLAGS := -mxl-soft-div -msoft-float -Wno-main -Wl,-no-check-sections -fno-zero-initialized-in-bss
+CFLAGS += -O2 -Wall
+DEB_FLAGS += -g
+AFLAGS := -D__ASSEMBLY__ $(CFLAGS)
+LDFLAGS := -static -nostdlib -relax -defsym _STACK_SIZE=0x0200
+
+OBJS := $(OUT)/start.o $(C_OBJS) $(A_OBJS)
+
+REQ_FIRMWARE       := $(OUT)/imem.bin $(OUT)/imem.asm $(OUT)/dmem.bin $(OUT)/firmware.lst
+
+FIRMWARE_DIR := .
+
+USB_APP_VID_PID ?= 0x1669:0x1023
+
+USB_SENDHEX := ./usb_sendhex
+
+#===============================================================================
+
+# Attempt to create a output directory.
+$(shell [ -d ${OUT} ] || mkdir -p ${OUT})
+
+# Verify if it was successful.
+OUTPUT_DIR := $(shell cd $(OUT) && /bin/pwd)
+$(if $(OUTPUT_DIR),,$(error output directory "$(OUT)" does not exist))
+
+#===============================================================================
+
+.PHONY: all
+all: firmware
+
+#$(OUT)/%.o: $(FIRMWARE_DIR)/%.c
+#      $(TARGET_CC) $(CFLAGS) $(DEB_FLAGS) -c $< -o $@
+
+$(OUT)/%.s: $(FIRMWARE_DIR)/%.c
+       $(TARGET_CC) $(CFLAGS) $(DEB_FLAGS) -S $< -o $@
+
+.PRECIOUS: $(OUT)/%.s
+
+$(OUT)/%.o: $(OUT)/%.s
+       $(TARGET_CC) $(AFLAGS) -fpreprocessed -c $< -o $@
+
+$(OUT)/%.o: $(FIRMWARE_DIR)/%.S
+       $(TARGET_CC) $(AFLAGS) $(DEB_FLAGS) -c $< -o $@
+
+$(OUT)/firmware.elf: $(OBJS)
+       $(TARGET_LD) $(LDFLAGS) -T $(FIRMWARE_DIR)/utils/tumbl.ld-script -o $@ $(OBJS)
+
+.PHONY: re-firmware
+re-firmware $(REQ_FIRMWARE): $(REQ_PKG) $(OUT)/firmware.elf
+       $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .text -S $(OUT)/imem.bin
+       $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .data -S $(OUT)/dmem.bin
+       $(TARGET_OBJDUMP) -DSCz $(OUT)/firmware.elf > $(OUT)/firmware.lst
+       cd $(OUT); \
+       $(TARGET_OBJDUMP) -b binary -mmbtumbl -EB -D imem.bin | sed -e 's/.data/.text/' > imem.asm
+
+#===============================================================================
+
+.PHONY: clean
+clean:
+       rm -rf $(OUT)
+
+.PHONY: firmware
+firmware: $(REQ_FIRMWARE)
+
+.PHONY: install-tumbl
+install-tumbl: $(USB_SENDHEX) $(BUILDDIR)/imem.bin $(BUILDDIR)/dmem.bin
+       $(USB_SENDHEX) -d $(USB_APP_VID_PID) -c 0xF100 -a 0x0001
+       $(USB_SENDHEX) -d $(USB_APP_VID_PID) -t 3 -s 0x00000000 -f binary $(BUILDDIR)/imem.bin
+       $(USB_SENDHEX) -d $(USB_APP_VID_PID) -t 3 -s 0x00001000 -f binary $(BUILDDIR)/dmem.bin
+       $(USB_SENDHEX) -d $(USB_APP_VID_PID) -c 0xF100 -a 0x0000
+
+# imem
+# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80000000 -l 0x200 -f dump -u -
+# dmem
+# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80001000 -l 0x200 -f dump -u -
+# PC
+# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80003008 -l 0x4 -f dump -u -

diff --git a/hw/tb/firmware-for-xmem-bug/firmware.c b/hw/tb/firmware-for-xmem-bug/firmware.c
new file mode 100644 (file)
index 0000000..88c2a77
--- /dev/null
+++ b/hw/tb/firmware-for-xmem-bug/firmware.c
@@ -0,0 +1,36 @@
+/*******************************************************************
+  Components for embedded applications builded for
+  laboratory and medical instruments firmware
+
+  firmware.c - Firmware to test Tumbl xmem bus access
+
+  (C) 2001-2014 by Pavel Pisa pisa@cmp.felk.cvut.cz
+  (C) 2002-2014 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#include <stdint.h>
+#include "tumbl_addr.h"
+
+int32_t sin_res;
+int32_t cos_res;
+
+void init_defvals(void)
+{
+}
+
+void main(void)
+{
+  while (1) {
+    uint32_t dummy;
+
+    *FPGA_FNCAPPROX_SIN = 0x30000000;
+    dummy = *FPGA_FNCAPPROX_SIN;
+    dummy = *FPGA_FNCAPPROX_SIN;
+    dummy = *FPGA_FNCAPPROX_SIN;
+    sin_res = *FPGA_FNCAPPROX_SIN;
+    dummy = *FPGA_FNCAPPROX_COS;
+    cos_res = *FPGA_FNCAPPROX_COS;
+    asm volatile("": : : "memory");
+  }
+}

diff --git a/hw/tb/firmware-for-xmem-bug/start.S b/hw/tb/firmware-for-xmem-bug/start.S
new file mode 100644 (file)
index 0000000..065542f
--- /dev/null
+++ b/hw/tb/firmware-for-xmem-bug/start.S
@@ -0,0 +1,29 @@
+/* LX ROCON firmware reduced startup file */
+
+.globl _main
+.align 2
+
+_main:
+
+       /* Stack pointer */
+       addi     r1, r0, 0xFFC
+
+       /* reset data */
+       addi     r6, r0, _sdata
+       addi     r7, r0, _edata
+       rsub     r18, r6, r7
+       brci     le, r18, .Lenddata
+.Lloopdata:
+       swi      r0, r6, 0
+       addi     r6, r6, 4
+       rsub     r18, r6, r7
+       brci     gt, r18, .Lloopdata
+.Lenddata:
+       /* Init default values */
+       brli     r15, init_defvals
+
+       /* Run program */
+       brli     r15, main
+
+       /* End of program */
+       halt     0

diff --git a/hw/tb/firmware-for-xmem-bug/tumbl_addr.h b/hw/tb/firmware-for-xmem-bug/tumbl_addr.h
new file mode 100644 (file)
index 0000000..649858e
--- /dev/null
+++ b/hw/tb/firmware-for-xmem-bug/tumbl_addr.h
@@ -0,0 +1,85 @@
+#ifndef _TUMBL_ADDR_H
+#define _TUMBL_ADDR_H
+
+#include <stdint.h>
+
+#ifndef IOPORT32BIT
+ #define IO32ADDR(_val) ((volatile uint32_t *)(_val))
+#endif /*IOPORT32BIT*/
+
+#define FPGA_IRC_BASE           0x00002000
+
+#define FPGA_IRC0               IO32ADDR(FPGA_IRC_BASE+0x0000)
+#define FPGA_IRC1               IO32ADDR(FPGA_IRC_BASE+0x0008)
+#define FPGA_IRC2               IO32ADDR(FPGA_IRC_BASE+0x0010)
+#define FPGA_IRC3               IO32ADDR(FPGA_IRC_BASE+0x0018)
+#define FPGA_IRC4               IO32ADDR(FPGA_IRC_BASE+0x0020)
+#define FPGA_IRC5               IO32ADDR(FPGA_IRC_BASE+0x0028)
+#define FPGA_IRC6               IO32ADDR(FPGA_IRC_BASE+0x0030)
+#define FPGA_IRC7               IO32ADDR(FPGA_IRC_BASE+0x0038)
+
+#define FPGA_FNCAPPROX_BASE     0x00003000
+
+#define FPGA_FNCAPPROX          IO32ADDR(FPGA_FNCAPPROX_BASE)
+#define FPGA_FNCAPPROX_RECI     IO32ADDR(FPGA_FNCAPPROX_BASE+0x04)
+#define FPGA_FNCAPPROX_SIN      IO32ADDR(FPGA_FNCAPPROX_BASE+0x08)
+#define FPGA_FNCAPPROX_COS      IO32ADDR(FPGA_FNCAPPROX_BASE+0x0c)
+
+#define FPGA_LX_MASTER_BASE     0x00004000
+
+#define FPGA_LX_MASTER_TX       IO32ADDR(FPGA_LX_MASTER_BASE+0x0000)
+
+/* pwm_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) + chan; */
+
+#define FPGA_LX_MASTER_TX_PWM0  (FPGA_LX_MASTER_TX+9)
+#define FPGA_LX_MASTER_TX_PWM1  (FPGA_LX_MASTER_TX+10)
+#define FPGA_LX_MASTER_TX_PWM2  (FPGA_LX_MASTER_TX+11)
+#define FPGA_LX_MASTER_TX_PWM3  (FPGA_LX_MASTER_TX+12)
+#define FPGA_LX_MASTER_TX_PWM4  (FPGA_LX_MASTER_TX+13)
+#define FPGA_LX_MASTER_TX_PWM5  (FPGA_LX_MASTER_TX+14)
+#define FPGA_LX_MASTER_TX_PWM6  (FPGA_LX_MASTER_TX+15)
+#define FPGA_LX_MASTER_TX_PWM7  (FPGA_LX_MASTER_TX+16)
+
+#define FPGA_LX_MASTER_TX_PWM8  (FPGA_LX_MASTER_TX+18)
+#define FPGA_LX_MASTER_TX_PWM9  (FPGA_LX_MASTER_TX+19)
+#define FPGA_LX_MASTER_TX_PWM10 (FPGA_LX_MASTER_TX+20)
+#define FPGA_LX_MASTER_TX_PWM11 (FPGA_LX_MASTER_TX+21)
+#define FPGA_LX_MASTER_TX_PWM12 (FPGA_LX_MASTER_TX+22)
+#define FPGA_LX_MASTER_TX_PWM13 (FPGA_LX_MASTER_TX+23)
+#define FPGA_LX_MASTER_TX_PWM14 (FPGA_LX_MASTER_TX+24)
+#define FPGA_LX_MASTER_TX_PWM15 (FPGA_LX_MASTER_TX+25)
+
+#define FPGA_LX_MASTER_RX       IO32ADDR(FPGA_LX_MASTER_BASE+0x0800)
+
+/* rec_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) * 3 + chan * 2; */
+
+#define FPGA_LX_MASTER_RX_ADC0  (FPGA_LX_MASTER_RX+9)
+#define FPGA_LX_MASTER_RX_ADC1  (FPGA_LX_MASTER_RX+11)
+#define FPGA_LX_MASTER_RX_ADC2  (FPGA_LX_MASTER_RX+13)
+#define FPGA_LX_MASTER_RX_ADC3  (FPGA_LX_MASTER_RX+15)
+#define FPGA_LX_MASTER_RX_ADC4  (FPGA_LX_MASTER_RX+17)
+#define FPGA_LX_MASTER_RX_ADC5  (FPGA_LX_MASTER_RX+19)
+#define FPGA_LX_MASTER_RX_ADC6  (FPGA_LX_MASTER_RX+21)
+#define FPGA_LX_MASTER_RX_ADC7  (FPGA_LX_MASTER_RX+23)
+
+#define FPGA_LX_MASTER_RX_VIN   (FPGA_LX_MASTER_RX+25)
+
+#define FPGA_LX_MASTER_RX_ADC8  (FPGA_LX_MASTER_RX+28)
+#define FPGA_LX_MASTER_RX_ADC9  (FPGA_LX_MASTER_RX+30)
+#define FPGA_LX_MASTER_RX_ADC10 (FPGA_LX_MASTER_RX+32)
+#define FPGA_LX_MASTER_RX_ADC11 (FPGA_LX_MASTER_RX+34)
+#define FPGA_LX_MASTER_RX_ADC12 (FPGA_LX_MASTER_RX+36)
+#define FPGA_LX_MASTER_RX_ADC13 (FPGA_LX_MASTER_RX+38)
+#define FPGA_LX_MASTER_RX_ADC14 (FPGA_LX_MASTER_RX+40)
+#define FPGA_LX_MASTER_RX_ADC15 (FPGA_LX_MASTER_RX+42)
+
+#define FPGA_LX_MASTER_CTRL     IO32ADDR(FPGA_LX_MASTER_BASE+0x1000)
+
+#define FPGA_LX_MASTER_RESET    (FPGA_LX_MASTER_CTRL+0)
+#define FPGA_LX_MASTER_TX_REG   (FPGA_LX_MASTER_CTRL+1)
+#define FPGA_LX_MASTER_TX_WDOG  (FPGA_LX_MASTER_CTRL+2)
+#define FPGA_LX_MASTER_TX_CYCLE (FPGA_LX_MASTER_CTRL+3)
+#define FPGA_LX_MASTER_RX_REG   (FPGA_LX_MASTER_CTRL+4)
+#define FPGA_LX_MASTER_RX_DDIV  (FPGA_LX_MASTER_CTRL+5)
+
+#endif /* _TUMBL_ADDR_H */

diff --git a/hw/tb/imem.bits b/hw/tb/imem.bits
new file mode 100644 (file)
index 0000000..f1636bb
--- /dev/null
+++ b/hw/tb/imem.bits
@@ -0,0 +1,25 @@
+00100000001000000000111111111100
+00100000110000000000000000000000
+00100000111000000000000000000000
+00000110010001100011100000000000
+10111100011100100000000000010100
+11111000000001100000000000000000
+00100000110001100000000000000100
+00000110010001100011100000000000
+10111100100100101111111111110100
+10111001111001000000000000001100
+10111001111001000000000000001100
+11111100000000000000000000000000
+10110100000011110000000000000100
+10110000000000000011000000000000
+00110000101000000000000000000000
+11111000101000000011000000001000
+11101000011000000011000000001000
+11101000011000000011000000001000
+11101000011000000011000000001000
+11101000100000000011000000001000
+11101000011000000011000000001100
+11101000011000000011000000001100
+11111000100000000000000000000000
+11111000011000000000000000000100
+10111000000000001111111111011100

diff --git a/hw/tb/test-rocon.gtkw b/hw/tb/test-rocon.gtkw
new file mode 100644 (file)
index 0000000..9eb743c
--- /dev/null
+++ b/hw/tb/test-rocon.gtkw
@@ -0,0 +1,80 @@
+[*]
+[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
+[*] Tue Dec 30 01:29:16 2014
+[*]
+[dumpfile] "test-rocon.ghw"
+[dumpfile_mtime] "Tue Dec 30 00:57:38 2014"
+[dumpfile_size] 308909
+[savefile] "test-rocon.gtkw"
+[timestart] 9059500000
+[size] 1480 1076
+[pos] -1 -1
+*-25.226513 9150700000 9190000000 9126000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[markername] AError
+[markername] BBad read
+[treeopen] top.
+[treeopen] top.lx_rocon_top_tb.
+[treeopen] top.lx_rocon_top_tb.uut.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.i_ramb.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_exeq.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_gprf.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_gprf.i_rd.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.
+[treeopen] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.xmemb_i.
+[sst_width] 356
+[signals_width] 276
+[sst_expanded] 1
+[sst_vpaned_height] 322
+@28
+top.lx_rocon_top_tb.clk_50m
+@22
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[31:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[31] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[30] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[29] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[28] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[27] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[26] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[25] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[24] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[23] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[22] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[21] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[20] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[19] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[18] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[17] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[16] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[15] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[14] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[13] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[12] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[11] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[10] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[9] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[8] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[7] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[6] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[5] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.pc_o[0]
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[31:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[31] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[30] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[29] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[28] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[27] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[26] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[25] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[24] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[23] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[22] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[21] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[20] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[19] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[18] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[17] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[16] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[15] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[14] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[13] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[12] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[11] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[10] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[9] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[8] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[7] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[6] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[5] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_data_i[0]
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[8:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[8] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[7] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[6] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[5] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_addr_i[0]
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_we_i[3:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_we_i[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_we_i[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_we_i[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.imem_we_i[0]
+@28
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.xmemb_i.clken
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_ctrl.reset_s
+top.lx_rocon_top_tb.uut.init_s
+top.lx_rocon_top_tb.uut.tumbl_ce_s
+@22
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[11:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[11] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[10] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[9] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[8] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[7] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[6] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[5] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.address_i[0]
+@28
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.ce_i
+@200
+-dmem
+@22
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[9:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[9] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[8] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[7] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[6] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[5] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.adr_i[0]
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.bls_i[3:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.bls_i[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.bls_i[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.bls_i[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.bls_i[0]
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[31:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[31] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[30] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[29] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[28] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[27] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[26] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[25] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[24] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[23] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[22] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[21] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[20] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[19] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[18] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[17] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[16] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[15] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[14] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[13] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[12] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[11] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[10] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[9] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[8] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[7] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[6] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[5] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.dat_i[0]
+@28
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.ce_i
+@22
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.i_ramb.wea[3:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.i_ramb.wea[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.i_ramb.wea[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.i_ramb.wea[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_dmem.i_ramb.wea[0]
+@28
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem2ctrl_o.clken
+@200
+-fncapprox
+@28
+top.lx_rocon_top_tb.uut.function_approx.next_ce_i
+@22
+#{top.lx_rocon_top_tb.uut.function_approx.address_i[4:0]} top.lx_rocon_top_tb.uut.function_approx.address_i[4] top.lx_rocon_top_tb.uut.function_approx.address_i[3] top.lx_rocon_top_tb.uut.function_approx.address_i[2] top.lx_rocon_top_tb.uut.function_approx.address_i[1] top.lx_rocon_top_tb.uut.function_approx.address_i[0]
+#{top.lx_rocon_top_tb.uut.function_approx.bls_i[3:0]} top.lx_rocon_top_tb.uut.function_approx.bls_i[3] top.lx_rocon_top_tb.uut.function_approx.bls_i[2] top.lx_rocon_top_tb.uut.function_approx.bls_i[1] top.lx_rocon_top_tb.uut.function_approx.bls_i[0]
+#{top.lx_rocon_top_tb.uut.function_approx.data_i[31:0]} top.lx_rocon_top_tb.uut.function_approx.data_i[31] top.lx_rocon_top_tb.uut.function_approx.data_i[30] top.lx_rocon_top_tb.uut.function_approx.data_i[29] top.lx_rocon_top_tb.uut.function_approx.data_i[28] top.lx_rocon_top_tb.uut.function_approx.data_i[27] top.lx_rocon_top_tb.uut.function_approx.data_i[26] top.lx_rocon_top_tb.uut.function_approx.data_i[25] top.lx_rocon_top_tb.uut.function_approx.data_i[24] top.lx_rocon_top_tb.uut.function_approx.data_i[23] top.lx_rocon_top_tb.uut.function_approx.data_i[22] top.lx_rocon_top_tb.uut.function_approx.data_i[21] top.lx_rocon_top_tb.uut.function_approx.data_i[20] top.lx_rocon_top_tb.uut.function_approx.data_i[19] top.lx_rocon_top_tb.uut.function_approx.data_i[18] top.lx_rocon_top_tb.uut.function_approx.data_i[17] top.lx_rocon_top_tb.uut.function_approx.data_i[16] top.lx_rocon_top_tb.uut.function_approx.data_i[15] top.lx_rocon_top_tb.uut.function_approx.data_i[14] top.lx_rocon_top_tb.uut.function_approx.data_i[13] top.lx_rocon_top_tb.uut.function_approx.data_i[12] top.lx_rocon_top_tb.uut.function_approx.data_i[11] top.lx_rocon_top_tb.uut.function_approx.data_i[10] top.lx_rocon_top_tb.uut.function_approx.data_i[9] top.lx_rocon_top_tb.uut.function_approx.data_i[8] top.lx_rocon_top_tb.uut.function_approx.data_i[7] top.lx_rocon_top_tb.uut.function_approx.data_i[6] top.lx_rocon_top_tb.uut.function_approx.data_i[5] top.lx_rocon_top_tb.uut.function_approx.data_i[4] top.lx_rocon_top_tb.uut.function_approx.data_i[3] top.lx_rocon_top_tb.uut.function_approx.data_i[2] top.lx_rocon_top_tb.uut.function_approx.data_i[1] top.lx_rocon_top_tb.uut.function_approx.data_i[0]
+#{top.lx_rocon_top_tb.uut.function_approx.data_o[31:0]} top.lx_rocon_top_tb.uut.function_approx.data_o[31] top.lx_rocon_top_tb.uut.function_approx.data_o[30] top.lx_rocon_top_tb.uut.function_approx.data_o[29] top.lx_rocon_top_tb.uut.function_approx.data_o[28] top.lx_rocon_top_tb.uut.function_approx.data_o[27] top.lx_rocon_top_tb.uut.function_approx.data_o[26] top.lx_rocon_top_tb.uut.function_approx.data_o[25] top.lx_rocon_top_tb.uut.function_approx.data_o[24] top.lx_rocon_top_tb.uut.function_approx.data_o[23] top.lx_rocon_top_tb.uut.function_approx.data_o[22] top.lx_rocon_top_tb.uut.function_approx.data_o[21] top.lx_rocon_top_tb.uut.function_approx.data_o[20] top.lx_rocon_top_tb.uut.function_approx.data_o[19] top.lx_rocon_top_tb.uut.function_approx.data_o[18] top.lx_rocon_top_tb.uut.function_approx.data_o[17] top.lx_rocon_top_tb.uut.function_approx.data_o[16] top.lx_rocon_top_tb.uut.function_approx.data_o[15] top.lx_rocon_top_tb.uut.function_approx.data_o[14] top.lx_rocon_top_tb.uut.function_approx.data_o[13] top.lx_rocon_top_tb.uut.function_approx.data_o[12] top.lx_rocon_top_tb.uut.function_approx.data_o[11] top.lx_rocon_top_tb.uut.function_approx.data_o[10] top.lx_rocon_top_tb.uut.function_approx.data_o[9] top.lx_rocon_top_tb.uut.function_approx.data_o[8] top.lx_rocon_top_tb.uut.function_approx.data_o[7] top.lx_rocon_top_tb.uut.function_approx.data_o[6] top.lx_rocon_top_tb.uut.function_approx.data_o[5] top.lx_rocon_top_tb.uut.function_approx.data_o[4] top.lx_rocon_top_tb.uut.function_approx.data_o[3] top.lx_rocon_top_tb.uut.function_approx.data_o[2] top.lx_rocon_top_tb.uut.function_approx.data_o[1] top.lx_rocon_top_tb.uut.function_approx.data_o[0]
+@200
+-mem_wrb
+@28
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.wrb_action
+@22
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[31:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[31] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[30] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[29] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[28] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[27] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[26] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[25] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[24] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[23] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[22] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[21] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[20] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[19] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[18] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[17] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[16] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[15] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[14] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[13] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[12] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[11] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[10] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[9] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[8] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[7] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[6] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[5] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.data_rd[0]
+#{top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.wrix_rd[4:0]} top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.wrix_rd[4] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.wrix_rd[3] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.wrix_rd[2] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.wrix_rd[1] top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_mem.mem_wrb_o.wrix_rd[0]
+@28
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_gprf.i_rd.web[0]
+top.lx_rocon_top_tb.uut.memory_bus_tumbl.i_tumbl.i_gprf.i_rd.clkb
+[pattern_trace] 1
+[pattern_trace] 0