7 #define IO32ADDR(_val) ((volatile uint32_t *)(_val))
10 #define FPGA_IRC_BASE 0x00002000
12 #define FPGA_IRC0 IO32ADDR(FPGA_IRC_BASE+0x0000)
13 #define FPGA_IRC1 IO32ADDR(FPGA_IRC_BASE+0x0008)
14 #define FPGA_IRC2 IO32ADDR(FPGA_IRC_BASE+0x0010)
15 #define FPGA_IRC3 IO32ADDR(FPGA_IRC_BASE+0x0018)
16 #define FPGA_IRC4 IO32ADDR(FPGA_IRC_BASE+0x0020)
17 #define FPGA_IRC5 IO32ADDR(FPGA_IRC_BASE+0x0028)
18 #define FPGA_IRC6 IO32ADDR(FPGA_IRC_BASE+0x0030)
19 #define FPGA_IRC7 IO32ADDR(FPGA_IRC_BASE+0x0038)
21 #define FPGA_FNCAPPROX_BASE 0x00003000
23 #define FPGA_FNCAPPROX IO32ADDR(FPGA_FNCAPPROX_BASE)
24 #define FPGA_FNCAPPROX_RECI IO32ADDR(FPGA_FNCAPPROX_BASE+0x04)
25 #define FPGA_FNCAPPROX_SIN IO32ADDR(FPGA_FNCAPPROX_BASE+0x08)
26 #define FPGA_FNCAPPROX_COS IO32ADDR(FPGA_FNCAPPROX_BASE+0x0c)
28 #define FPGA_LX_MASTER_BASE 0x00004000
30 #define FPGA_LX_MASTER_TX IO32ADDR(FPGA_LX_MASTER_BASE+0x0000)
32 /* pwm_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) + chan; */
34 #define FPGA_LX_MASTER_TX_PWM0 (FPGA_LX_MASTER_TX+9)
35 #define FPGA_LX_MASTER_TX_PWM1 (FPGA_LX_MASTER_TX+10)
36 #define FPGA_LX_MASTER_TX_PWM2 (FPGA_LX_MASTER_TX+11)
37 #define FPGA_LX_MASTER_TX_PWM3 (FPGA_LX_MASTER_TX+12)
38 #define FPGA_LX_MASTER_TX_PWM4 (FPGA_LX_MASTER_TX+13)
39 #define FPGA_LX_MASTER_TX_PWM5 (FPGA_LX_MASTER_TX+14)
40 #define FPGA_LX_MASTER_TX_PWM6 (FPGA_LX_MASTER_TX+15)
41 #define FPGA_LX_MASTER_TX_PWM7 (FPGA_LX_MASTER_TX+16)
43 #define FPGA_LX_MASTER_TX_PWM8 (FPGA_LX_MASTER_TX+18)
44 #define FPGA_LX_MASTER_TX_PWM9 (FPGA_LX_MASTER_TX+19)
45 #define FPGA_LX_MASTER_TX_PWM10 (FPGA_LX_MASTER_TX+20)
46 #define FPGA_LX_MASTER_TX_PWM11 (FPGA_LX_MASTER_TX+21)
47 #define FPGA_LX_MASTER_TX_PWM12 (FPGA_LX_MASTER_TX+22)
48 #define FPGA_LX_MASTER_TX_PWM13 (FPGA_LX_MASTER_TX+23)
49 #define FPGA_LX_MASTER_TX_PWM14 (FPGA_LX_MASTER_TX+24)
50 #define FPGA_LX_MASTER_TX_PWM15 (FPGA_LX_MASTER_TX+25)
52 #define FPGA_LX_MASTER_RX IO32ADDR(FPGA_LX_MASTER_BASE+0x0800)
54 /* rec_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) * 3 + chan * 2; */
56 #define FPGA_LX_MASTER_RX_ADC0 (FPGA_LX_MASTER_RX+9)
57 #define FPGA_LX_MASTER_RX_ADC1 (FPGA_LX_MASTER_RX+11)
58 #define FPGA_LX_MASTER_RX_ADC2 (FPGA_LX_MASTER_RX+13)
59 #define FPGA_LX_MASTER_RX_ADC3 (FPGA_LX_MASTER_RX+15)
60 #define FPGA_LX_MASTER_RX_ADC4 (FPGA_LX_MASTER_RX+17)
61 #define FPGA_LX_MASTER_RX_ADC5 (FPGA_LX_MASTER_RX+19)
62 #define FPGA_LX_MASTER_RX_ADC6 (FPGA_LX_MASTER_RX+21)
63 #define FPGA_LX_MASTER_RX_ADC7 (FPGA_LX_MASTER_RX+23)
65 #define FPGA_LX_MASTER_RX_VIN (FPGA_LX_MASTER_RX+25)
67 #define FPGA_LX_MASTER_RX_ADC8 (FPGA_LX_MASTER_RX+28)
68 #define FPGA_LX_MASTER_RX_ADC9 (FPGA_LX_MASTER_RX+30)
69 #define FPGA_LX_MASTER_RX_ADC10 (FPGA_LX_MASTER_RX+32)
70 #define FPGA_LX_MASTER_RX_ADC11 (FPGA_LX_MASTER_RX+34)
71 #define FPGA_LX_MASTER_RX_ADC12 (FPGA_LX_MASTER_RX+36)
72 #define FPGA_LX_MASTER_RX_ADC13 (FPGA_LX_MASTER_RX+38)
73 #define FPGA_LX_MASTER_RX_ADC14 (FPGA_LX_MASTER_RX+40)
74 #define FPGA_LX_MASTER_RX_ADC15 (FPGA_LX_MASTER_RX+42)
76 #define FPGA_LX_MASTER_CTRL IO32ADDR(FPGA_LX_MASTER_BASE+0x1000)
78 #define FPGA_LX_MASTER_RESET (FPGA_LX_MASTER_CTRL+0)
79 #define FPGA_LX_MASTER_TX_REG (FPGA_LX_MASTER_CTRL+1)
80 #define FPGA_LX_MASTER_TX_WDOG (FPGA_LX_MASTER_CTRL+2)
81 #define FPGA_LX_MASTER_TX_CYCLE (FPGA_LX_MASTER_CTRL+3)
82 #define FPGA_LX_MASTER_RX_REG (FPGA_LX_MASTER_CTRL+4)
83 #define FPGA_LX_MASTER_RX_DDIV (FPGA_LX_MASTER_CTRL+5)
85 #endif /* _TUMBL_ADDR_H */