2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
5 use ieee.numeric_std.all;
9 -- Entities within lx_rocon
11 package lx_rocon_pkg is
14 type IRC_INPUT_Type is record
20 type IRC_COUNT_OUTPUT_Type is record
21 qcount : std_logic_vector(7 downto 0);
22 index : std_logic_vector(7 downto 0);
23 index_event : std_logic;
26 type IRC_STATE_OUTPUT_Type is record
29 index_event : std_logic;
33 type IRC_OUTPUT_Type is record
34 count : IRC_COUNT_OUTPUT_Type;
35 state : IRC_STATE_OUTPUT_Type;
39 type IRC_INPUT_Array_Type is array (natural range <>) of IRC_INPUT_Type;
40 type IRC_OUTPUT_Array_Type is array (natural range <>) of IRC_OUTPUT_Type;
41 type IRC_COUNT_OUTPUT_Array_Type is array (natural range <>) of IRC_COUNT_OUTPUT_Type;
42 type IRC_STATE_OUTPUT_Array_Type is array (natural range <>) of IRC_STATE_OUTPUT_Type;
44 -- IRC coprocessor MAIN
45 component irc_proc_main
48 num_irc_g : positive := 4
54 reset_i : in std_logic;
56 irc_i : in IRC_COUNT_OUTPUT_Array_Type((num_irc_g-1) downto 0);
58 irc_index_reset_o : out std_logic_vector((num_irc_g-1) downto 0);
60 mem_clk_i : in std_logic;
61 mem_en_i : in std_logic;
62 mem_we_i : in std_logic_vector(3 downto 0);
63 mem_addr_i : in std_logic_vector(ceil_log2(num_irc_g) downto 0);
64 mem_data_i : in std_logic_vector(31 downto 0);
65 mem_data_o : out std_logic_vector(31 downto 0)
69 -- IRC coprocessor INC
70 component irc_proc_inc
73 num_irc_g : positive := 4
79 reset_i : in std_logic;
81 op_o : out std_logic_vector(1 downto 0);
82 axis_o : out std_logic_vector((ceil_log2(num_irc_g)-1) downto 0)
92 reset_i : in std_logic;
93 irc_i : in IRC_INPUT_Type;
95 reset_index_event_i : in std_logic;
96 reset_index_event2_i : in std_logic;
97 reset_ab_error_i : in std_logic;
99 irc_o : out IRC_OUTPUT_Type
108 clk_i : in std_logic;
109 reset_i : in std_logic;
110 a0_i, b0_i : in std_logic;
111 index0_i : in std_logic;
113 reset_index_event_i : in std_logic;
114 reset_index_event2_i : in std_logic;
115 reset_ab_error_i : in std_logic;
117 qcount_o : out std_logic_vector(7 downto 0);
118 qcount_index_o : out std_logic_vector(7 downto 0);
119 index_o : out std_logic;
120 index_event_o : out std_logic;
121 index_event2_o : out std_logic;
122 a_rise_o, a_fall_o : out std_logic;
123 b_rise_o, b_fall_o : out std_logic;
124 ab_event_o : out std_logic;
125 ab_error_o : out std_logic
129 -- D sampler (filtered, 2 cycles)
133 clk_i : in std_logic;
139 -- D sampler (filtered, 3 cycles)
143 clk_i : in std_logic;
153 clk_i : in std_logic;
154 reset_i : in std_logic;
155 input_i : in std_logic;
156 crc_o : out std_logic_vector(7 downto 0)
163 cnt_width_g : natural := 8
167 clk_i : in std_logic;
169 reset_i : in std_logic;
170 ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);
171 q_out_o : out std_logic
175 -- LX Master transmitter
176 component lxmaster_transmitter
178 cycle_cnt_width_g : natural := 12
182 clk_i : in std_logic;
183 reset_i : in std_logic;
185 clock_o : out std_logic;
186 mosi_o : out std_logic;
187 sync_o : out std_logic;
189 register_i : in std_logic;
190 register_o : out std_logic_vector(1 downto 0);
191 register_we_i : in std_logic;
193 cycle_reg_i : in std_logic_vector(cycle_cnt_width_g-1 downto 0);
194 cycle_reg_o : out std_logic_vector(cycle_cnt_width_g-1 downto 0);
195 cycle_reg_we_i : in std_logic;
197 wdog_i : in std_logic;
198 wdog_we_i : in std_logic;
200 mem_clk_i : in std_logic;
201 mem_en_i : in std_logic;
202 mem_we_i : in std_logic_vector(1 downto 0);
203 mem_addr_i : in std_logic_vector(8 downto 0);
204 mem_data_i : in std_logic_vector(15 downto 0);
205 mem_data_o : out std_logic_vector(15 downto 0)
209 -- LX Master receiver
210 component lxmaster_receiver
213 clk_i : in std_logic;
214 reset_i : in std_logic;
216 clock_i : in std_logic;
217 miso_i : in std_logic;
218 sync_i : in std_logic;
219 -- Receive done pulse
220 rx_done_o : out std_logic;
222 register_i : in std_logic;
223 register_o : out std_logic_vector(1 downto 0);
224 register_we_i : in std_logic;
226 mem_clk_i : in std_logic;
227 mem_en_i : in std_logic;
228 mem_we_i : in std_logic_vector(1 downto 0);
229 mem_addr_i : in std_logic_vector(8 downto 0);
230 mem_data_i : in std_logic_vector(15 downto 0);
231 mem_data_o : out std_logic_vector(15 downto 0)
235 -- LX math functions approximation
237 component lx_fncapprox
240 clk_i : in std_logic;
241 reset_i : in std_logic;
243 address_i : in std_logic_vector(4 downto 0);
245 data_i : in std_logic_vector(31 downto 0);
246 data_o : out std_logic_vector(31 downto 0);
248 bls_i : in std_logic_vector(3 downto 0)
252 -- Clock Cross Domain Synchronization Elastic Buffer/FIFO
253 component lx_crosdom_ser_fifo
256 fifo_len_g : positive := 8;
257 sync_adj_g : integer := 0
261 -- Asynchronous clock domain interface
262 acd_clock_i : in std_logic;
263 acd_miso_i : in std_logic;
264 acd_sync_i : in std_logic;
266 clk_i : in std_logic;
267 reset_i : in std_logic;
268 -- Output synchronous with clk_i
269 miso_o : out std_logic;
270 sync_o : out std_logic;
271 data_ready_o : out std_logic
275 --------------------------------------------------------------------------------
277 --------------------------------------------------------------------------------
279 component lx_rocon_tumbl
282 IMEM_ABITS_g : positive := 11;
283 DMEM_ABITS_g : positive := 12;
285 USE_HW_MUL_g : boolean := true;
286 USE_BARREL_g : boolean := true;
287 COMPATIBILITY_MODE_g : boolean := false
291 clk_i : in std_logic;
292 rst_i : in std_logic;
293 halt_i : in std_logic;
294 int_i : in std_logic;
295 trace_i : in std_logic;
296 trace_kick_i : in std_logic;
298 pc_o : out std_logic_vector(31 downto 0);
299 -- Internal halt (remove with trace kick)
300 halted_o : out std_logic;
301 halt_code_o : out std_logic_vector(4 downto 0);
302 -- Internal memory (instruction)
303 imem_clk_i : in std_logic;
304 imem_en_i : in std_logic;
305 imem_we_i : in std_logic_vector(3 downto 0);
306 imem_addr_i : in std_logic_vector(8 downto 0);
307 imem_data_i : in std_logic_vector(31 downto 0);
308 imem_data_o : out std_logic_vector(31 downto 0);
309 -- Internal memory (data)
310 dmem_clk_i : in std_logic;
311 dmem_en_i : in std_logic;
312 dmem_we_i : in std_logic_vector(3 downto 0);
313 dmem_addr_i : in std_logic_vector(9 downto 0);
314 dmem_data_i : in std_logic_vector(31 downto 0);
315 dmem_data_o : out std_logic_vector(31 downto 0);
316 -- External memory bus
317 xmemb_sel_o : out std_logic;
318 xmemb_i : in DMEMB2CORE_Type;
319 xmemb_o : out CORE2DMEMB_Type
323 component lx_rocon_imem
326 -- Memory wiring for Tumbl
327 clk_i : in std_logic;
329 adr_i : in std_logic_vector(10 downto 2);
330 dat_o : out std_logic_vector(31 downto 0);
331 -- Memory wiring for Master CPU
332 clk_m : in std_logic;
334 we_m : in std_logic_vector(3 downto 0);
335 addr_m : in std_logic_vector(8 downto 0);
336 din_m : in std_logic_vector(31 downto 0);
337 dout_m : out std_logic_vector(31 downto 0)
341 component lx_rocon_dmem
344 -- Memory wiring for Tumbl
345 clk_i : in std_logic;
347 adr_i : in std_logic_vector(11 downto 2);
348 bls_i : in std_logic_vector(3 downto 0);
349 dat_i : in std_logic_vector(31 downto 0);
350 dat_o : out std_logic_vector(31 downto 0);
351 -- Memory wiring for Master CPU
352 clk_m : in std_logic;
354 we_m : in std_logic_vector(3 downto 0);
355 addr_m : in std_logic_vector(9 downto 0);
356 din_m : in std_logic_vector(31 downto 0);
357 dout_m : out std_logic_vector(31 downto 0)
361 component lx_rocon_gprf_abd
364 clk_i : in std_logic;
365 rst_i : in std_logic;
366 clken_i : in std_logic;
367 gprf_finish_wrb_mem_i : in std_logic;
369 ID2GPRF_i : in ID2GPRF_Type;
370 MEM_WRB_i : in WRB_Type;
371 GPRF2EX_o : out GPRF2EX_Type
375 --------------------------------------------------------------------------------
377 --------------------------------------------------------------------------------
379 -- Measurement register
380 component measurement_register
383 id_g : std_logic_vector(31 downto 0) := (others => '0')
388 clk_i : in std_logic;
390 reset_i : in std_logic;
394 switch_i : in std_logic;
396 data_i : in std_logic_vector(31 downto 0);
397 data_o : out std_logic_vector(31 downto 0);
399 bls_i : in std_logic_vector(3 downto 0)
407 clk_i : in std_logic;
408 reset_i : in std_logic;
410 address_i : in std_logic_vector(4 downto 0);
412 data_i : in std_logic_vector(31 downto 0);
413 data_o : out std_logic_vector(31 downto 0);
415 bls_i : in std_logic_vector(3 downto 0);
417 irc_i : in IRC_INPUT_Array_Type(7 downto 0)
421 -- Measurement interconnect
422 component bus_measurement
426 clk_i : in std_logic;
428 reset_i : in std_logic;
432 address_i : in std_logic_vector(1 downto 0);
434 data_i : in std_logic_vector(31 downto 0);
435 data_o : out std_logic_vector(31 downto 0);
437 bls_i : in std_logic_vector(3 downto 0)
441 -- Tumbl interconnect
446 clk_i : in std_logic;
450 reset_i : in std_logic;
451 -- Master CPU bus for the memory
452 bls_i : in std_logic_vector(3 downto 0);
453 address_i : in std_logic_vector(11 downto 0);
454 data_i : in std_logic_vector(31 downto 0);
455 data_o : out std_logic_vector(31 downto 0);
456 -- Tumbl extrenal memory bus
457 xmemb_sel_o : out std_logic;
458 xmemb_i : in DMEMB2CORE_Type;
459 xmemb_o : out CORE2DMEMB_Type
463 -- Register on the bus
464 component bus_register is
468 reset_value_g : std_logic_vector(31 downto 0) := (others => '0');
478 clk_i : in std_logic;
480 reset_i : in std_logic;
484 data_i : in std_logic_vector((b0_g+b1_g+b2_g+b3_g-1) downto 0);
485 data_o : out std_logic_vector((b0_g+b1_g+b2_g+b3_g-1) downto 0);
487 bls_i : in std_logic_vector(3 downto 0)
491 -- LX Master bus interconnect
492 component bus_lxmaster
495 clk_i : in std_logic;
496 reset_i : in std_logic;
498 address_i : in std_logic_vector(10 downto 0);
500 data_i : in std_logic_vector(15 downto 0);
501 data_o : out std_logic_vector(15 downto 0);
503 bls_i : in std_logic_vector(1 downto 0);
505 rx_done_o : out std_logic;
506 -- Signals for LX Master
507 clock_i : in std_logic;
508 miso_i : in std_logic;
509 sync_i : in std_logic;
511 clock_o : out std_logic;
512 mosi_o : out std_logic;
513 sync_o : out std_logic
517 --------------------------------------------------------------------------------
519 --------------------------------------------------------------------------------
520 type BRAM_type is (READ_FIRST, WRITE_FIRST, NO_CHANGE);
522 component xilinx_dualport_bram
525 byte_width : positive := 8;
526 address_width : positive := 8;
527 we_width : positive := 4;
528 port_a_type : BRAM_type := READ_FIRST;
529 port_b_type : BRAM_type := READ_FIRST
536 wea : in std_logic_vector((we_width-1) downto 0);
537 addra : in std_logic_vector((address_width-1) downto 0);
538 dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
539 douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
543 web : in std_logic_vector((we_width-1) downto 0);
544 addrb : in std_logic_vector((address_width-1) downto 0);
545 dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
546 doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
552 package body lx_rocon_pkg is