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[fpga/lx-cpu1/lx-rocon.git] / hw / measurement_register.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
5 use ieee.numeric_std.all;
6 use work.lx_rocon_pkg.all;
7
8 -- Transaction measurement register
9
10 entity measurement_register is
11         generic
12         (
13                 id_g   : std_logic_vector(31 downto 0) := (others => '0')
14         );
15         port
16         (
17                 -- Clock
18                 clk_i    : in std_logic;
19                 -- Reset
20                 reset_i  : in std_logic;
21                 -- Chip enable
22                 ce_i     : in std_logic;
23                 -- Switch
24                 switch_i : in std_logic;
25                 -- Data bus
26                 data_i   : in std_logic_vector(31 downto 0);
27                 data_o   : out std_logic_vector(31 downto 0);
28                 -- Bus signals
29                 bls_i    : in std_logic_vector(3 downto 0)
30         );
31 end measurement_register;
32
33 architecture Behavioral of measurement_register is
34         signal value_s : std_logic_vector(31 downto 0);
35 begin
36
37         data_o <= value_s when switch_i = '1' else id_g;
38
39 -- Write waits for clock
40 memory_bus_write:
41         process
42         begin
43
44                 wait until clk_i'event and clk_i = '1';
45
46                 if reset_i = '1' then
47                         value_s <= (others => '0');
48                 else
49
50                         if ce_i = '1' and bls_i /= "0000" then
51
52                                 if bls_i(0) = '1' then
53                                         value_s(7 downto 0)   <= data_i(7 downto 0);
54                                 end if;
55                                 if bls_i(1) = '1' then
56                                         value_s(15 downto 8)  <= data_i(15 downto 8);
57                                 end if;
58                                 if bls_i(2) = '1' then
59                                         value_s(23 downto 16) <= data_i(23 downto 16);
60                                 end if;
61                                 if bls_i(3) = '1' then
62                                         value_s(31 downto 24) <= data_i(31 downto 24);
63                                 end if;
64
65                         end if;
66                 end if;
67
68         end process;
69
70 end Behavioral;
71