hw/lx-rocon_tumbl/lx_rocon_tumbl.vhd

   1 library ieee;
   2
   3 use ieee.std_logic_1164.all;
   4 use ieee.std_logic_arith.all;
   5 use ieee.std_logic_unsigned.all;
   6 use ieee.numeric_std.all;
   7 use work.mbl_pkg.all;
   8 use work.lx_rocon_pkg.all;
   9
  10 -- Tumbl configured as a coprocessor for lx_rocon
  11 -- Uses 12 bits width address bus with HW barrel and multiplier
  12
  13 entity lx_rocon_tumbl is
  14         generic
  15         (
  16                 -- This is for 32-bit addressing
  17                 IMEM_ABITS_g         : positive := 9;
  18                 DMEM_ABITS_g         : positive := 10;
  19                 --
  20                 USE_HW_MUL_g         : boolean := true;
  21                 USE_BARREL_g         : boolean := true;
  22                 COMPATIBILITY_MODE_g : boolean := false
  23         );
  24         port
  25         (
  26                 clk_i        :  in std_logic;
  27                 rst_i        :  in std_logic;
  28           halt_i       :  in std_logic;
  29                 int_i        :  in std_logic;
  30                 trace_i      :  in std_logic;
  31                 trace_kick_i :  in std_logic;
  32                 -- Program counter
  33                 pc_o         : out std_logic_vector(31 downto 0);
  34                 -- Internal halt (remove with trace kick)
  35                 halted_o     : out std_logic;
  36                 halt_code_o  : out std_logic_vector(4 downto 0);
  37                 -- Internal memory (instruction)
  38                 imem_clk_i   : in std_logic;
  39     imem_en_i    : in std_logic;
  40     imem_we_i    : in std_logic_vector(3 downto 0);
  41     imem_addr_i  : in std_logic_vector(8 downto 0);
  42     imem_data_i  : in std_logic_vector(31 downto 0);
  43     imem_data_o  : out std_logic_vector(31 downto 0);
  44                 -- Internal memory (data)
  45                 dmem_clk_i   : in std_logic;
  46     dmem_en_i    : in std_logic;
  47     dmem_we_i    : in std_logic_vector(3 downto 0);
  48     dmem_addr_i  : in std_logic_vector(9 downto 0);
  49     dmem_data_i  : in std_logic_vector(31 downto 0);
  50     dmem_data_o  : out std_logic_vector(31 downto 0);
  51                 -- External memory bus
  52                 xmemb_sel_o  : out std_logic;
  53                 xmemb_i      : in DMEMB2CORE_Type;
  54                 xmemb_o      : out CORE2DMEMB_Type
  55         );
  56 end entity lx_rocon_tumbl;
  57
  58 architecture rtl of lx_rocon_tumbl is
  59
  60         constant DMEM_TEST_c : std_logic_vector((14-DMEM_ABITS_g) downto 0) := (others => '0');
  61
  62         signal imem_clken_s  : std_logic;
  63         signal imem_addr_s   : std_logic_vector((IMEM_ABITS_g-1) downto 0);
  64         signal imem_data_s   : std_logic_vector(31 downto 0);
  65         signal gprf_clken_s  : std_logic;
  66         signal gprf_finish_wrb_mem_s : std_logic;
  67         signal core_clken_s  : std_logic;
  68         signal pc_ctrl_s     : std_logic;
  69         signal c2dmemb_s     : CORE2DMEMB_Type;
  70         signal dmem_data_s   : std_logic_vector(31 downto 0);
  71         signal DMEMB_i_s     : DMEMB2CORE_Type;
  72
  73         signal MEM2CTRL_s    : MEM2CTRL_Type;
  74         signal INT_CTRL_s    : INT_CTRL_Type;
  75         signal ID2CTRL_s     : ID2CTRL_Type;
  76
  77         signal IF2ID_s,      IF2ID_r      : IF2ID_Type;
  78         signal ID2EX_s,      ID2EX_r      : ID2EX_Type;
  79         signal delay_bit_r                : std_logic;
  80         signal ID2GPRF_s                  : ID2GPRF_Type;
  81         signal GPRF2EX_s                  : GPRF2EX_Type;
  82         signal EX2IF_s,      EX2IF_r      : EX2IF_Type;
  83         signal EX2CTRL_s                  : EX2CTRL_Type;
  84         signal EX2MEM_s,     EX2MEM_r     : EX2MEM_Type;
  85         signal EX_WRB_s,     EX_WRB_r     : WRB_Type;
  86         signal MEM_WRB_s                  : WRB_Type;
  87         signal IMM_LOCK_s,   IMM_LOCK_r   : IMM_LOCK_Type;
  88         signal HAZARD_WRB_s, HAZARD_WRB_r : HAZARD_WRB_Type;
  89         signal EX2MSR_s                   : MSR_Type;
  90         signal MSR2EX_s                   : MSR_Type;
  91         signal MEM_REG_s,    MEM_REG_r    : MEM_REG_Type;
  92         signal dmem_sel_s,   dmem_sel_r   : std_logic;
  93         signal HALT_s                     : HALT_Type;
  94         signal ext_halt_s                 : std_logic;
  95
  96         signal imem_really_clken_s        : std_logic;
  97         signal dmem_really_sel_s          : std_logic;
  98         signal gprf_really_clken_s        : std_logic;
  99
 100
 101 begin
 102
 103         -- select internal data memory when all address bits above DMEM_ABITS_g are zero
 104         dmem_sel_s  <= '1' when (c2dmemb_s.addr(14 downto DMEM_ABITS_g) = DMEM_TEST_c)
 105                                                                         else '0';
 106         XMEMB_sel_o <= (not dmem_sel_s) and core_clken_s;
 107         XMEMB_o     <= c2dmemb_s;
 108         pc_o        <= ID2EX_r.program_counter; -- Program counter for EXEQ
 109         halted_o    <= HALT_s.halt;
 110         halt_code_o <= HALT_s.halt_code;
 111         ext_halt_s  <= halt_i;
 112
 113         imem_really_clken_s <= imem_clken_s and core_clken_s;
 114         dmem_really_sel_s   <= dmem_sel_s and core_clken_s;
 115         gprf_really_clken_s <= gprf_clken_s and core_clken_s;
 116
 117 I_IMEM: lx_rocon_imem
 118         port map
 119         (
 120                 clk_i  => clk_i,
 121                 cs_i   => imem_really_clken_s,
 122                 adr_i  => imem_addr_s((IMEM_ABITS_g-1) downto 0),
 123                 dat_o  => imem_data_s,
 124
 125                 clk_m  => imem_clk_i,
 126                 en_m   => imem_en_i,
 127                 we_m   => imem_we_i,
 128                 addr_m => imem_addr_i,
 129                 din_m  => imem_data_i,
 130                 dout_m => imem_data_o
 131         );
 132
 133 I_DMEM: lx_rocon_dmem
 134         port map
 135         (
 136                 clk_i  => clk_i,
 137                 ce_i   => dmem_really_sel_s,
 138                 adr_i  => c2dmemb_s.addr((DMEM_ABITS_g-1) downto 0),
 139                 bls_i  => c2dmemb_s.bls,
 140                 dat_i  => c2dmemb_s.data,
 141                 dat_o  => dmem_data_s,
 142
 143                 clk_m  => dmem_clk_i,
 144                 en_m   => dmem_en_i,
 145                 we_m   => dmem_we_i,
 146                 addr_m => dmem_addr_i,
 147                 din_m  => dmem_data_i,
 148                 dout_m => dmem_data_o
 149         );
 150
 151 I_FETCH: fetch
 152         port map
 153         (
 154                 prog_cntr_i => IF2ID_r.program_counter,
 155                 inc_pc_i    => pc_ctrl_s,
 156                 EX2IF_i     => EX2IF_r,
 157                 IF2ID_o     => IF2ID_s
 158         );
 159
 160 I_DECODE: decode
 161         generic map(USE_HW_MUL_g, USE_BARREL_g, COMPATIBILITY_MODE_g)
 162         port map
 163         (
 164                 IF2ID_i     => IF2ID_r,
 165                 imem_data_i => imem_data_s,
 166                 --
 167                 ID2GPRF_o   => ID2GPRF_s,
 168                 ID2EX_o     => ID2EX_s,
 169                 --
 170                 INT_CTRL_i  => INT_CTRL_s,
 171                 ID2CTRL_o   => ID2CTRL_s
 172         );
 173
 174 I_GPRF: lx_rocon_gprf_abd
 175         port map
 176         (
 177                 clk_i        => clk_i,
 178                 rst_i        => rst_i,
 179                 clken_i      => gprf_really_clken_s,
 180                 gprf_finish_wrb_mem_i => gprf_finish_wrb_mem_s,
 181                 --
 182                 ID2GPRF_i    => ID2GPRF_s,
 183                 MEM_WRB_i    => MEM_WRB_s,
 184                 GPRF2EX_o    => GPRF2EX_s
 185         );
 186
 187 I_EXEQ: exeq
 188         generic map(USE_HW_MUL_g, USE_BARREL_g, COMPATIBILITY_MODE_g)
 189         port map
 190         (
 191                 IF2ID_i      => IF2ID_r,
 192                 --
 193                 ID2EX_i      => ID2EX_r,
 194                 delayBit_i   => delay_bit_r,
 195                 GPRF2EX_i    => GPRF2EX_s,
 196                 EX2IF_o      => EX2IF_s,
 197                 EX2CTRL_o    => EX2CTRL_s,
 198                 HALT_o       => HALT_s,
 199                 --
 200                 EX_WRB_i     => EX_WRB_r,
 201                 EX_WRB_o     => EX_WRB_s,
 202                 MEM_WRB_i    => MEM_WRB_s,
 203                 --
 204                 HAZARD_WRB_i => HAZARD_WRB_r,
 205                 HAZARD_WRB_o => HAZARD_WRB_s,
 206                 --
 207                 IMM_LOCK_i   => IMM_LOCK_r,
 208                 IMM_LOCK_o   => IMM_LOCK_s,
 209                 --
 210                 MSR_i        => MSR2EX_s,
 211                 MSR_o        => EX2MSR_s,
 212                 --
 213                 EX2MEM_o     => EX2MEM_s
 214         );
 215
 216         -- this is a very simple address block decoder, just "internal" dmem or "external"
 217         -- clken and int hardwired for fast internal data-memory
 218         DMEMB_i_s.bus_wait  <= '0'     when (dmem_sel_s = '1') else XMEMB_i.bus_wait;
 219         DMEMB_i_s.bus_taken <= '0'     when (dmem_sel_s = '1') else XMEMB_i.bus_taken;
 220         DMEMB_i_s.data  <= dmem_data_s when (dmem_sel_r = '1') else XMEMB_i.data;
 221         DMEMB_i_s.int   <= XMEMB_i.int;
 222
 223 I_MEM: mem
 224         port map
 225         (
 226                 EX2MEM_i    => EX2MEM_r,
 227                 MEM_WRB_o   => MEM_WRB_s,
 228                 --
 229                 DMEMB_i     => DMEMB_i_s,
 230                 DMEMB_o     => c2dmemb_s,
 231                 --
 232                 MEM_REG_i  => MEM_REG_r,
 233                 MEM_REG_o  => MEM_REG_s,
 234                 --
 235                 MEM2CTRL_o => MEM2CTRL_s
 236         );
 237
 238 I_CTRL: core_ctrl
 239         generic map (IMEM_ABITS_g, COMPATIBILITY_MODE_g)
 240         port map
 241         (
 242                 clk_i           => clk_i,
 243                 rst_i           => rst_i,
 244                 halt_i          => ext_halt_s,
 245                 int_i           => int_i,
 246                 trace_i         => trace_i,
 247                 trace_kick_i    => trace_kick_i,
 248                 core_clken_o    => core_clken_s,
 249                 -- specific fetch i/o
 250                 imem_addr_o     => imem_addr_s,
 251                 imem_clken_o    => imem_clken_s,
 252                 pc_ctrl_o       => pc_ctrl_s,
 253                 -- fetch to decode pipeline registers
 254                 IF2ID_REG_i     => IF2ID_s,
 255                 IF2ID_REG_o     => IF2ID_r,
 256                 -- decode to exeq pipeline registers
 257                 ID2EX_REG_i     => ID2EX_s,
 258                 ID2EX_REG_o     => ID2EX_r,
 259                 delay_bit_o     => delay_bit_r,
 260                 -- GPRF control
 261                 gprf_clken_o    => gprf_clken_s,
 262                 gprf_finish_wrb_mem_o => gprf_finish_wrb_mem_s,
 263                 -- exeq to fetch feedback registers
 264                 EX2IF_REG_i     => EX2IF_s,
 265                 EX2IF_REG_o     => EX2IF_r,
 266                 EX2CTRL_REG_i   => EX2CTRL_s,
 267                 -- exeq to core (halting)
 268                 exeq_halt_i     => HALT_s.halt,
 269                 -- exeq to mem pipeline registers
 270                 EX2MEM_REG_i    => EX2MEM_s,
 271                 EX2MEM_REG_o    => EX2MEM_r,
 272                 -- mem pipeline register
 273                 MEM_REG_i       => MEM_REG_s,
 274                 MEM_REG_o       => MEM_REG_r,
 275                 -- decode control i/o
 276                 ID2CTRL_i       => ID2CTRL_s,
 277                 INT_CTRL_o      => INT_CTRL_s,
 278                 -- exeq control i/o
 279                 EX_WRB_i        => EX_WRB_s,
 280                 EX_WRB_o        => EX_WRB_r,
 281                 -- data hazard i/o
 282                 HAZARD_WRB_i    => HAZARD_WRB_s,
 283                 HAZARD_WRB_o    => HAZARD_WRB_r,
 284                 -- for handling the 'IMM' instruction
 285                 IMM_LOCK_i      => IMM_LOCK_s,
 286                 IMM_LOCK_o      => IMM_LOCK_r,
 287                 -- for handling the Machine Status Register
 288                 MSR_i           => EX2MSR_s,
 289                 MSR_o           => MSR2EX_s,
 290                 -- miscellaneous
 291                 MEM2CTRL_i      => MEM2CTRL_s
 292         );
 293
 294 regd_proc:
 295         process
 296         begin
 297                 wait until clk_i'event and clk_i = '1';
 298                 if (rst_i = '1') then           -- synchronous reset ...
 299                         dmem_sel_r   <= '1';
 300                 else                            -- delay select_external_mem (needed for reading ...)
 301                         dmem_sel_r <= dmem_sel_s;   -- OR c2dmemb_s.wre; ??
 302                 end if;
 303         end process regd_proc;
 304
 305 end architecture rtl;