2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;
4 use ieee.numeric_std.all;
8 -- Entities within lx_rocon
10 package lx_rocon_pkg is
13 type IRC_INPUT_Type is record
19 type IRC_COUNT_OUTPUT_Type is record
20 qcount : std_logic_vector(7 downto 0);
21 index : std_logic_vector(7 downto 0);
22 index_event : std_logic;
25 type IRC_STATE_OUTPUT_Type is record
28 index_event : std_logic;
32 type IRC_OUTPUT_Type is record
33 count : IRC_COUNT_OUTPUT_Type;
34 state : IRC_STATE_OUTPUT_Type;
38 type IRC_INPUT_Array_Type is array (natural range <>) of IRC_INPUT_Type;
39 type IRC_OUTPUT_Array_Type is array (natural range <>) of IRC_OUTPUT_Type;
40 type IRC_COUNT_OUTPUT_Array_Type is array (natural range <>) of IRC_COUNT_OUTPUT_Type;
41 type IRC_STATE_OUTPUT_Array_Type is array (natural range <>) of IRC_STATE_OUTPUT_Type;
43 -- IRC coprocessor MAIN
44 component irc_proc_main
47 num_irc_g : positive := 4
53 reset_i : in std_logic;
55 irc_i : in IRC_COUNT_OUTPUT_Array_Type((num_irc_g-1) downto 0);
57 irc_index_reset_o : out std_logic_vector((num_irc_g-1) downto 0);
59 mem_clk_i : in std_logic;
60 mem_en_i : in std_logic;
61 mem_we_i : in std_logic_vector(3 downto 0);
62 mem_addr_i : in std_logic_vector(ceil_log2(num_irc_g) downto 0);
63 mem_data_i : in std_logic_vector(31 downto 0);
64 mem_data_o : out std_logic_vector(31 downto 0)
68 -- IRC coprocessor INC
69 component irc_proc_inc
72 num_irc_g : positive := 4
78 reset_i : in std_logic;
80 op_o : out std_logic_vector(1 downto 0);
81 axis_o : out std_logic_vector((ceil_log2(num_irc_g)-1) downto 0)
91 reset_i : in std_logic;
92 irc_i : in IRC_INPUT_Type;
94 reset_index_event_i : in std_logic;
95 reset_index_event2_i : in std_logic;
96 reset_ab_error_i : in std_logic;
98 irc_o : out IRC_OUTPUT_Type
107 clk_i : in std_logic;
108 reset_i : in std_logic;
109 a0_i, b0_i : in std_logic;
110 index0_i : in std_logic;
112 reset_index_event_i : in std_logic;
113 reset_index_event2_i : in std_logic;
114 reset_ab_error_i : in std_logic;
116 qcount_o : out std_logic_vector(7 downto 0);
117 qcount_index_o : out std_logic_vector(7 downto 0);
118 index_o : out std_logic;
119 index_event_o : out std_logic;
120 index_event2_o : out std_logic;
121 a_rise_o, a_fall_o : out std_logic;
122 b_rise_o, b_fall_o : out std_logic;
123 ab_event_o : out std_logic;
124 ab_error_o : out std_logic
128 -- D sampler (filtered, 2 cycles)
132 clk_i : in std_logic;
138 -- D sampler (filtered, 3 cycles)
142 clk_i : in std_logic;
152 clk_i : in std_logic;
153 reset_i : in std_logic;
154 input_i : in std_logic;
155 crc_o : out std_logic_vector(7 downto 0)
162 cnt_width_g : natural := 8
166 clk_i : in std_logic;
168 reset_i : in std_logic;
169 ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);
170 q_out_o : out std_logic
174 -- LX Master transmitter
175 component lxmaster_transmitter
177 cycle_cnt_width_g : natural := 12
181 clk_i : in std_logic;
182 reset_i : in std_logic;
184 clock_o : out std_logic;
185 mosi_o : out std_logic;
186 sync_o : out std_logic;
188 register_i : in std_logic;
189 register_o : out std_logic_vector(1 downto 0);
190 register_we_i : in std_logic;
192 cycle_reg_i : in std_logic_vector(cycle_cnt_width_g-1 downto 0);
193 cycle_reg_o : out std_logic_vector(cycle_cnt_width_g-1 downto 0);
194 cycle_reg_we_i : in std_logic;
196 wdog_i : in std_logic;
197 wdog_we_i : in std_logic;
199 mem_clk_i : in std_logic;
200 mem_en_i : in std_logic;
201 mem_we_i : in std_logic_vector(1 downto 0);
202 mem_addr_i : in std_logic_vector(8 downto 0);
203 mem_data_i : in std_logic_vector(15 downto 0);
204 mem_data_o : out std_logic_vector(15 downto 0)
208 -- LX Master receiver
209 component lxmaster_receiver
212 clk_i : in std_logic;
213 reset_i : in std_logic;
215 clock_i : in std_logic;
216 miso_i : in std_logic;
217 sync_i : in std_logic;
218 -- Receive done pulse
219 rx_done_o : out std_logic;
221 register_i : in std_logic;
222 register_o : out std_logic_vector(1 downto 0);
223 register_we_i : in std_logic;
225 mem_clk_i : in std_logic;
226 mem_en_i : in std_logic;
227 mem_we_i : in std_logic_vector(1 downto 0);
228 mem_addr_i : in std_logic_vector(8 downto 0);
229 mem_data_i : in std_logic_vector(15 downto 0);
230 mem_data_o : out std_logic_vector(15 downto 0)
234 -- LX math functions approximation
236 component lx_fncapprox
239 clk_i : in std_logic;
240 reset_i : in std_logic;
242 address_i : in std_logic_vector(4 downto 0);
244 data_i : in std_logic_vector(31 downto 0);
245 data_o : out std_logic_vector(31 downto 0);
247 bls_i : in std_logic_vector(3 downto 0)
251 -- Clock Cross Domain Synchronization Elastic Buffer/FIFO
252 component lx_crosdom_ser_fifo
255 fifo_len_g : positive := 8;
256 sync_adj_g : integer := 0
260 -- Asynchronous clock domain interface
261 acd_clock_i : in std_logic;
262 acd_miso_i : in std_logic;
263 acd_sync_i : in std_logic;
265 clk_i : in std_logic;
266 reset_i : in std_logic;
267 -- Output synchronous with clk_i
268 miso_o : out std_logic;
269 sync_o : out std_logic;
270 data_ready_o : out std_logic
274 --------------------------------------------------------------------------------
276 --------------------------------------------------------------------------------
278 component lx_rocon_tumbl
281 IMEM_ABITS_g : positive := 11;
282 DMEM_ABITS_g : positive := 12;
284 USE_HW_MUL_g : boolean := true;
285 USE_BARREL_g : boolean := true;
286 COMPATIBILITY_MODE_g : boolean := false
290 clk_i : in std_logic;
291 rst_i : in std_logic;
292 halt_i : in std_logic;
293 int_i : in std_logic;
294 trace_i : in std_logic;
295 trace_kick_i : in std_logic;
297 pc_o : out std_logic_vector(31 downto 0);
298 -- Internal halt (remove with trace kick)
299 halted_o : out std_logic;
300 halt_code_o : out std_logic_vector(4 downto 0);
301 -- Internal memory (instruction)
302 imem_clk_i : in std_logic;
303 imem_en_i : in std_logic;
304 imem_we_i : in std_logic_vector(3 downto 0);
305 imem_addr_i : in std_logic_vector(8 downto 0);
306 imem_data_i : in std_logic_vector(31 downto 0);
307 imem_data_o : out std_logic_vector(31 downto 0);
308 -- Internal memory (data)
309 dmem_clk_i : in std_logic;
310 dmem_en_i : in std_logic;
311 dmem_we_i : in std_logic_vector(3 downto 0);
312 dmem_addr_i : in std_logic_vector(9 downto 0);
313 dmem_data_i : in std_logic_vector(31 downto 0);
314 dmem_data_o : out std_logic_vector(31 downto 0);
315 -- External memory bus
316 xmemb_sel_o : out std_logic;
317 xmemb_i : in DMEMB2CORE_Type;
318 xmemb_o : out CORE2DMEMB_Type
322 component lx_rocon_imem
325 -- Memory wiring for Tumbl
326 clk_i : in std_logic;
328 adr_i : in std_logic_vector(10 downto 2);
329 dat_o : out std_logic_vector(31 downto 0);
330 -- Memory wiring for Master CPU
331 clk_m : in std_logic;
333 we_m : in std_logic_vector(3 downto 0);
334 addr_m : in std_logic_vector(8 downto 0);
335 din_m : in std_logic_vector(31 downto 0);
336 dout_m : out std_logic_vector(31 downto 0)
340 component lx_rocon_dmem
343 -- Memory wiring for Tumbl
344 clk_i : in std_logic;
346 adr_i : in std_logic_vector(11 downto 2);
347 bls_i : in std_logic_vector(3 downto 0);
348 dat_i : in std_logic_vector(31 downto 0);
349 dat_o : out std_logic_vector(31 downto 0);
350 -- Memory wiring for Master CPU
351 clk_m : in std_logic;
353 we_m : in std_logic_vector(3 downto 0);
354 addr_m : in std_logic_vector(9 downto 0);
355 din_m : in std_logic_vector(31 downto 0);
356 dout_m : out std_logic_vector(31 downto 0)
360 component lx_rocon_gprf_abd
363 clk_i : in std_logic;
364 rst_i : in std_logic;
365 clken_i : in std_logic;
366 gprf_finish_wrb_mem_i : in std_logic;
368 ID2GPRF_i : in ID2GPRF_Type;
369 MEM_WRB_i : in WRB_Type;
370 GPRF2EX_o : out GPRF2EX_Type
374 --------------------------------------------------------------------------------
376 --------------------------------------------------------------------------------
378 -- Measurement register
379 component measurement_register
382 id_g : std_logic_vector(31 downto 0) := (others => '0')
387 clk_i : in std_logic;
389 reset_i : in std_logic;
393 switch_i : in std_logic;
395 data_i : in std_logic_vector(31 downto 0);
396 data_o : out std_logic_vector(31 downto 0);
398 bls_i : in std_logic_vector(3 downto 0)
406 clk_i : in std_logic;
407 reset_i : in std_logic;
409 address_i : in std_logic_vector(4 downto 0);
411 data_i : in std_logic_vector(31 downto 0);
412 data_o : out std_logic_vector(31 downto 0);
414 bls_i : in std_logic_vector(3 downto 0);
416 irc_i : in IRC_INPUT_Array_Type(7 downto 0)
420 -- Measurement interconnect
421 component bus_measurement
425 clk_i : in std_logic;
427 reset_i : in std_logic;
431 address_i : in std_logic_vector(1 downto 0);
433 data_i : in std_logic_vector(31 downto 0);
434 data_o : out std_logic_vector(31 downto 0);
436 bls_i : in std_logic_vector(3 downto 0)
440 -- Tumbl interconnect
445 clk_i : in std_logic;
449 reset_i : in std_logic;
450 -- Master CPU bus for the memory
451 bls_i : in std_logic_vector(3 downto 0);
452 address_i : in std_logic_vector(11 downto 0);
453 data_i : in std_logic_vector(31 downto 0);
454 data_o : out std_logic_vector(31 downto 0);
455 -- Tumbl extrenal memory bus
456 xmemb_sel_o : out std_logic;
457 xmemb_i : in DMEMB2CORE_Type;
458 xmemb_o : out CORE2DMEMB_Type
462 -- Register on the bus
463 component bus_register is
467 reset_value_g : std_logic_vector(31 downto 0) := (others => '0');
477 clk_i : in std_logic;
479 reset_i : in std_logic;
483 data_i : in std_logic_vector((b0_g+b1_g+b2_g+b3_g-1) downto 0);
484 data_o : out std_logic_vector((b0_g+b1_g+b2_g+b3_g-1) downto 0);
486 bls_i : in std_logic_vector(3 downto 0)
490 -- LX Master bus interconnect
491 component bus_lxmaster
494 clk_i : in std_logic;
495 reset_i : in std_logic;
497 address_i : in std_logic_vector(10 downto 0);
499 data_i : in std_logic_vector(15 downto 0);
500 data_o : out std_logic_vector(15 downto 0);
502 bls_i : in std_logic_vector(1 downto 0);
504 rx_done_o : out std_logic;
505 -- Signals for LX Master
506 clock_i : in std_logic;
507 miso_i : in std_logic;
508 sync_i : in std_logic;
510 clock_o : out std_logic;
511 mosi_o : out std_logic;
512 sync_o : out std_logic
516 --------------------------------------------------------------------------------
518 --------------------------------------------------------------------------------
519 type BRAM_type is (READ_FIRST, WRITE_FIRST, NO_CHANGE);
521 component xilinx_dualport_bram
524 byte_width : positive := 8;
525 address_width : positive := 8;
526 we_width : positive := 4;
527 port_a_type : BRAM_type := READ_FIRST;
528 port_b_type : BRAM_type := READ_FIRST
535 wea : in std_logic_vector((we_width-1) downto 0);
536 addra : in std_logic_vector((address_width-1) downto 0);
537 dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
538 douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
542 web : in std_logic_vector((we_width-1) downto 0);
543 addrb : in std_logic_vector((address_width-1) downto 0);
544 dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
545 doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
551 package body lx_rocon_pkg is